Hanno Scharwächter

A code-generator generator for Multi-Output Instructions

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

ASIP architecture exploration for efficient IPSec encryption: A case study

Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, 2004, TECS.

An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A methodology and tool suite for C compiler generation from ADL processor models

Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Instruction set customization of application specific processors for network processing: a case study

Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study

Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, 2004, SCOPES.

A novel approach for flexible and consistent ADL-driven ASIP design

Rainer Leupers, Heinrich Meyr, Weihua Sheng, 2004, Proceedings. 41st Design Automation Conference, 2004..

Fast graph‐based instruction selection for multi‐output instructions

Rainer Leupers, Yunheung Paek, Jongwon Lee, 2011, Softw. Pract. Exp..

Automatic identification and utilization of custom instructions for network processors

Hanno Scharwächter, 2016 .

A retargetable framework for compiler/architecture co-development

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2011, Des. Autom. Embed. Syst..

MAPS: An integrated framework for MPSoC application parallelization

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2008, 2008 45th ACM/IEEE Design Automation Conference.