W. Bae

发表

Double‐Layer‐Stacked One Diode‐One Resistive Switching Memory Crossbar Array with an Extremely High Rectification Ratio of 109

Yeong Jae Kwon, C. S. Hwang, J. Yoon, 2017 .

Comprehensive Writing Margin Analysis and its Application to Stacked one Diode‐One Memory Device for High‐Density Crossbar Resistance Switching Random Access Memory

D. Jeong, C. S. Hwang, K. J. Yoon, 2016 .

A Novel Stateful Logic Device and Circuit for In‐Memory Parity Programming in Crossbar Memory

Jin-woo Han, K. J. Yoon, W. Bae, 2020, Advanced Electronic Materials.

Selector Requirements for 3D Resistive Switching Crossbar Array Based on Writing Margin Evaluation

Woorham Bae, Cheol Seong Hwang, Kyung Jean Yoon, 2016 .

BAG2: A process-portable framework for generator-based AMS circuit design

Elad Alon, Borivoje Nikolic, Zhongkai Wang, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Today’s computing challenges: opportunities for computer hardware design

W. Bae, 2021, PeerJ Comput. Sci..

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies

Elad Alon, Borivoje Nikolić, Jaeduk Han, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Test of the VCSEL driver based on Verilog-A VCSEL model

Yoonsoo Kim, Gyungock Kim, D. Jeong, 2015, 2015 International SoC Design Conference (ISOCC).

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis

Deog-Kyoon Jeong, Borivoje Nikolić, Woorham Bae, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

Kannan Ramchandran, Elad Alon, Borivoje Nikolić, 2019, IEEE Journal of Solid-State Circuits.

CMOS Inverter as Analog Circuit: An Overview

Woorham Bae, W. Bae, 2019, Journal of Low Power Electronics and Applications.

Reference Spur Reduction Techniques for a Phase-Locked Loop

Deog-Kyoon Jeong, Gyu-Seob Jeong, Han-Gon Ko, 2019, IEEE Access.

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

Deog-Kyoon Jeong, Haram Ju, Kwanseo Park, 2016, IEEE Journal of Solid-State Circuits.

Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal–Oxide–Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network‐Based Stochastic Learning

Kyung Jean Yoon, Woorham Bae, K. J. Yoon, 2020, Adv. Intell. Syst..

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET

Elad Alon, Borivoje Nikolic, Woo-Rham Bae, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).