Manuel Valencia-Barrero

发表

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

Raúl Jiménez, Antonio J. Acosta, Jorge Juan-Chico, 2000, PATMOS.

HALOTIS: High Accuracy Logic TIming simulator with inertial and degradation delay model

Antonio J. Acosta, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Modular Asynchronous Arbiter Insensitive to Metastability

José Luis Huertas, Santiago Sánchez-Solano, Antonio J. Acosta, 1995, IEEE Trans. Computers.

New CMOS VLSI linear self-timed architectures

José Luis Huertas, Angel Barriga, Antonio J. Acosta, 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

A switching noise vision of the optimization techniques for low-power synthesis

Javier Castro-Ramirez, Manuel Valencia-Barrero, Pilar Parra Fernández, 2007, 2007 18th European Conference on Circuit Theory and Design.

A new faster method for calculating the resolution coefficient of CMOS latches: Design of an optimum latch

José Luis Huertas, Angel Barriga, Antonio J. Acosta, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Logic Synthesis

Angel Barriga, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández, 2008, Wiley Encyclopedia of Computer Science and Engineering.

Asymmetric clock driver for improved power and noise performances

Antonio J. Acosta, Javier Castro-Ramirez, Manuel Valencia-Barrero, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher

Manuel Valencia-Barrero, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández, 2018, 2018 Conference on Design of Circuits and Integrated Systems (DCIS).

Asynchronous Modular Arbiter

Manuel Valencia-Barrero, J. Calvo, J. I. Acha, 1986, IEEE Transactions on Computers.

Modeling of real bistables in VHDL

José Luis Huertas, Angel Barriga, Antonio J. Acosta, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

Gate-level simulation of CMOS circuits using the IDDM model

Antonio J. Acosta, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Selective Clock-Gating for Low-Power Synchronous Counters

Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero, 2005, J. Low Power Electron..

Degradation Delay Model Extension to CMOS Gates

Antonio J. Acosta, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, 2000, PATMOS.

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations

José Miguel Mora-Gutierrez, Erica Tena-Sánchez, Manuel Valencia-Barrero, 2021, Sensors.

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1

Antonio J. Acosta, Manuel Valencia-Barrero, Pilar Parra Fernández, 2002, PATMOS.