K. Kenis

发表

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Christopher J. Wilson, B. T. Chan, H. Mertens, 2020, IEEE Transactions on Electron Devices.

Challenges and novel approaches for photo resist removal and post-etch residue removal for 22 nm interconnects

G. Beyer, Z. Tokei, P. Mertens, 2009, 2009 IEEE International Interconnect Technology Conference.

Silicon surface metal contamination measurements using grazing-emission XRF spectrometry

M. Heyns, S. Gendt, P. Mertens, 1997 .

Use of Surface Haze for Evaluation of Photoresist Residue Removal Efficiency

S. Halder, K. Kenis, T. Bearda, 2009, IEEE Transactions on Semiconductor Manufacturing.

The Improvement of Subthreshold Slope and Transconductance of p-Type Bulk Si Field-Effect Transistors by Solid-Source Doping

N. Horiguchi, T. Chiarella, Y. Kikuchi, 2017, IEEE Transactions on Electron Devices.

Advanced cleaning for the growth of ultrathin gate oxide

M. Heyns, T. Bearda, R. Vos, 1999 .

Surface Passivation for Si Solar Cells: A Combination of Advanced Surface Cleaning and Thermal Atomic Layer Deposition of Al2O3

Robert Mertens, Jef Poortmans, Bart Vermang, 2012 .

Implementation of the IMEC-Clean in advanced CMOS manufacturing

M. Heyns, R. Vos, M. Meuris, 1999, 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314).

Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

H. Mertens, R. Ritzenthaler, M. Kim, 2018, International Electron Devices Meeting.

Particle Removal Efficiency and Damage Analysis on Silicon Wafers after Megasonic Cleaning in Solvents

K. Wostyn, T. Bearda, P. Mertens, 2009 .

A detailed study of semiconductor wafer drying

T. Bearda, W. Fyen, P. Mertens, 2008 .

Impact of Organic Contamination on Thin Gate Oxide Quality

M. Heyns, M. Meuris, S. Gendt, 1998 .

Chapter 19 – A Detailed Study of Semiconductor Wafer Drying

T. Bearda, W. Fyen, P. Mertens, 2008 .

Smooth and high quality epitaxial strained Ge grown on SiGe strain relaxed buffers with 70–85% Ge

R. Loo, P. Ong, P. Storck, 2011 .

Surface Passivation for Si Solar Cells: A Combination of Advanced Surface Cleaning and Thermal Atomic Layer Deposition of Al2O3

K. Wostyn, T. Bearda, R. Mertens, 2012 .

Megasonic, Non-Contact Cleaning Followed by 'Rotagoni' Drying of CMP Wafers

M. Heyns, W. Fyen, P. Mertens, 2001 .

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

On the Impact of Grown-in Silicon Oxide Precipitate Nuclei on Silicon Gate Oxide Integrity

J. Vanhellemont, D. Gräf, M. Depas, 1996 .

Scaled, Novel Effective Workfunction Metal Gate Stacks for Advanced Low-VT, Gate-All-Around Vertically Stacked Nanosheet FETs with Reduced Vertical Distance between Sheets

H. Mertens, R. Ritzenthaler, M. Kim, 2019, Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials.

Evaluation of Time‐of‐Flight Secondary Ion Mass Spectrometry for Metal Contamination Monitoring on Si Wafer Surfaces

Wilfried Vandervorst, S. De Gendt, Renaat Gijbels, 2000 .

Spectroscopy: a new route towards critical-dimension metrology of the cavity etch of nanosheet transistors

T. Nuytten, D. Van Den Heuvel, Y. Oniki, 2021, Advanced Lithography.

Low Temperature SiGe Steam Oxide - Aqueous Hf and NH3/NF3 Remote Plasma Etching and its Implementation as Si GAA Inner Spacer

H. Mertens, A. Hikavyy, K. Wostyn, 2018, Solid State Phenomena.

HF-Last Wet Clean in Combination with a Low Temperature GeH4-Assisted HCl In Situ Clean Prior to Si0.8Ge0.2-on-Si Epitaxial Growth

A. Hikavyy, K. Wostyn, B. Douhard, 2014 .

Optimized Post-CMP and Pre-Epi Cleans to Enable Smooth and High Quality Epitaxial Strained Ge Growth on SiGe Strain Relaxed Buffers

R. Loo, P. Ong, L. Souriau, 2012 .

A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation

K. Wostyn, D. Mocuta, N. Horiguchi, 2019, 2019 Symposium on VLSI Technology.

Ice-VII-like Structure Observed By XRD in Water Confined in Silica Nanoholes

K. Wostyn, G. Vereecke, K. Kenis, 2022, ECS Transactions.

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

H. Mertens, R. Ritzenthaler, Z. Tao, 2020, 2020 IEEE Symposium on VLSI Technology.

Impact of Iron Contamination and Roughness Generated in Ammonia Hydrogen Peroxide Mixtures (SC1) on 5 nm Gate Oxides

M. Heyns, S. Gendt, P. Mertens, 1998 .

Buried power rail integration for CMOS scaling beyond the 3 nm node

H. Mertens, Z. Tao, G. Mannaert, 2022, Advanced Lithography.

Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies

A. Vais, N. Collaert, N. Horiguchi, 2019, Advanced Lithography.

New bending mode in SAQP Si fins and its mitigation

K. Barla, A. Sepúlveda, K. Kenis, 2022, Materials Science in Semiconductor Processing.

Aging Phenomena in the Removal of Nano-Particles from Si Wafers

C. Vinckier, P. Mertens, G. Vereecke, 2007 .

Study of the Dynamics of Local Particle Removal Efficiencies Using Localized Haze Maps

K. Wostyn, T. Bearda, P. Mertens, 2007 .