V. Sharma

A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, V. Chikarmane, R. Heussner, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Intrinsic transistor reliability improvements from 22nm tri-gate technology

A. Rahman, S. Ramey, C. Auth, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).