R. Kim

Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node

M. H. van der Veen, J. Bekaert, K. Croes, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Track height reduction for standard-cell in below 5nm node: how low can you go?

J. Ryckaert, D. Verkest, P. Raghavan, 2018, Advanced Lithography.

Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

Diederik Verkest, Peter Debacker, Julien Ryckaert, 2019, Advanced Lithography.

CFET standard-cell design down to 3Track height for node 3nm and below

Diederik Verkest, Peter Debacker, Julien Ryckaert, 2019, Advanced Lithography.

Self-aligned block technology: a step toward further scaling

Carlos Fonseca, Chris Wilson, Julien Ryckaert, 2017, Advanced Lithography.