Kai Wang

Clock Network Sizing in Presence of Power Supply Noise

M. Marek-Sadowska, Kai Wang, 2004 .

On-chip power-supply network optimization using multigrid-based technique

Malgorzata Marek-Sadowska, Kai Wang, M. Marek-Sadowska, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On-chip power supply network optimization using multigrid-based technique

Kai Wang, M. Marek-Sadowska, M. Marek-Sadowska, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

General skew constrained clock network sizing based on sequential linear programming

Malgorzata Marek-Sadowska, Kai Wang, Yajun Ran, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Buffer sizing for clock power minimization subject to general skew constraints

Malgorzata Marek-Sadowska, Kai Wang, M. Marek-Sadowska, 2004, Proceedings. 41st Design Automation Conference, 2004..

Clock skew bounds estimation under power supply and process variations

Malgorzata Marek-Sadowska, Kai Wang, Hailin Jiang, 2005, ACM Great Lakes Symposium on VLSI.