W. Deng

发表

A 25MHz–6.44GHz LC-VCO using a 5-port inductor for multi-band frequency generation

K. Okada, A. Matsuzawa, W. Deng, 2011, 2011 IEEE Radio Frequency Integrated Circuits Symposium.

A constant-current-controlled class-C VCO using a self-adjusting replica biasing scheme

K. Okada, A. Matsuzawa, W. Deng, 2013, 2013 European Microwave Integrated Circuit Conference.

A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit

Kenichi Okada, Akira Matsuzawa, Teerachot Siriburanon, 2015, IEICE transactions on electronics.

A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition

Kenichi Okada, Akira Matsuzawa, Wei Deng, 2012, IEICE Trans. Electron..

A 60-GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD,(invited)

Akira Matsuzawa, Tomohiro Ueno, Teerachot Siriburanon, 2014 .

A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections

Kenichi Okada, Ning Li, Akira Matsuzawa, 2015, IEICE Trans. Electron..

A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS

Kenichi Okada, Hanli Liu, Akira Matsuzawa, 2018, IEICE Trans. Electron..

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI

Kenichi Okada, Akira Matsuzawa, Rui Wu, 2017, IEICE Trans. Electron..

C-12-9 A Fully Synthesized Fractional-N IL-PLL Using Only Digital Library

Akira Matsuzawa, Teerachot Siriburanon, Wei Deng, 2016 .

Frequency Synthesis Technique for 60 GHz Multi-Gbps Wireless

Kenichi Okada, Hanli Liu, Akira Matsuzawa, 2018, IoT and Low-Power Wireless.

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI

Kenichi Okada, Akira Matsuzawa, Rui Wu, 2016, IEICE Trans. Electron..

16.1 A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS

Kenichi Okada, Teerachot Siriburanon, Zheng Sun, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS

Baoyong Chi, Luqiang Duan, Ruichang Ma, 2021, 2021 Symposium on VLSI Circuits.

A tail-feedback VCO with self-adjusting current modulation scheme

Kenichi Okada, Akira Matsuzawa, Wei Deng, 2014, 2014 44th European Microwave Conference.

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2013, IEEE Journal of Solid-State Circuits.

A pulse-driven LC-VCO with a figure-of-merit of −192dBc/Hz

Kenichi Okada, Akira Matsuzawa, Aravind Tharayil Narayanan, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing

Kenichi Okada, Akira Matsuzawa, Wei Deng, 2013, IEEE Journal of Solid-State Circuits.

A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing

Kenichi Okada, Akira Matsuzawa, Wei Deng, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

A 39GHz 64-Element Phased-Array CMOS Transceiver with Built-in Calibration for Large-Array 5G NR

Yun Wang, Rui Wu, Bangan Liu, 2019, 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A CMOS 76–81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator

Wei Deng, Jianxi Wu, Nan Qi, 2020, IEEE Journal of Solid-State Circuits.

A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver

Kenichi Okada, Hanli Liu, Zheng Sun, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A 91.9-113.2 GHz Compact Frequency Tripler with 44.6 dBc Peak Fundamental Harmonic-Rejection-Ratio Using Embedded Notch-filters and Area-Efficient Matching Network in 65 nm CMOS

B. Chi, Haikun Jia, W. Deng, 2023, 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology

Baoyong Chi, Wei Deng, Zhijie Chen, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer

B. Chi, Haikun Jia, W. Deng, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

A current-reuse Class-C LC-VCO with an adaptive bias scheme

Kenichi Okada, Akira Matsuzawa, Teerachot Siriburanon, 2013, 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A D-Band Joint Radar-Communication CMOS Transceiver

B. Chi, Haikun Jia, W. Deng, 2023, IEEE Journal of Solid-State Circuits.

A Capacitor-less Digital LDO using Ripple-Frequency-Adaptive Time-domain Digital Pre-distortion Technique

B. Chi, Rui Wu, Haikun Jia, 2022, International Symposium on Security in Computing and Communications.

Transceiver SoC for Wireless Indoor Sensing Data-fusion

B. Chi, Haikun Jia, W. Deng, 2023, 2023 IEEE Custom Integrated Circuits Conference (CICC).

A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation

B. Chi, Zhihua Wang, Haikun Jia, 2022, IEEE Journal of Solid-State Circuits.

An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator

Baoyong Chi, Rui Wu, Haikun Jia, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS

Baoyong Chi, Haikun Jia, Zhihua Wang, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer

Zheng Song, Ruichang Ma, Wei Deng, 2020, IEEE Journal of Solid-State Circuits.

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad

Kenichi Okada, Hanli Liu, Akira Matsuzawa, 2016, IEEE Journal of Solid-State Circuits.

An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique

Baoyong Chi, Haikun Jia, Zhihua Wang, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase $\text{Noise +20}\text{logN}_{\mathrm{d}\mathrm{i}\mathrm{v}}$

B. Chi, Haikun Jia, Jiajie Tang, 2022, European Solid-State Circuits Conference.

A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS

B. Chi, Haikun Jia, W. Deng, 2023, IEEE Journal of Solid-State Circuits.

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2016, IEEE Journal of Solid-State Circuits.

A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2013, IEICE Trans. Electron..

A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS

B. Chi, Haikun Jia, W. Deng, 2022, 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA).

A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator

B. Chi, Haikun Jia, W. Deng, 2023, 2023 IEEE International Symposium on Circuits and Systems (ISCAS).

A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2016, IEEE Journal of Solid-State Circuits.

A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD

Kenichi Okada, Wei Deng, Bangan Liu, 2019, IEEE Solid-State Circuits Letters.

A Sub-mW Fractional- ${N}$ ADPLL With FOM of −246 dB for IoT Applications

Kenichi Okada, Dexian Tang, Huy Cu Ngo, 2018, IEEE Journal of Solid-State Circuits.

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Kenichi Okada, Hanli Liu, Zhijie Chen, 2018, IEEE Journal of Solid-State Circuits.

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2014, IEEE Journal of Solid-State Circuits.

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2015, IEEE Journal of Solid-State Circuits.

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2014, IEEE Journal of Solid-State Circuits.

An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS

Kenichi Okada, Hanli Liu, Akira Matsuzawa, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Bangan Liu, Huy Cu Ngo, Wei Deng, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular

Kenichi Okada, Hanli Liu, Akira Matsuzawa, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A Compact Square-Geometry Quad-Core 19 GHz Class-F VCO with Parallel Inductor-sharing Technique achieving -137.2 dBc/Hz Phase Noise at 10MHz Offset

B. Chi, Haikun Jia, W. Deng, 2022, 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch

Dexian Tang, Wei Deng, Hanli Liu, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS

B. Chi, Haikun Jia, W. Deng, 2022, IEEE Custom Integrated Circuits Conference.

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS

B. Chi, Haikun Jia, W. Deng, 2023, IEEE Custom Integrated Circuits Conference.

A 33.5–37.5-GHz Four-Element Phased-Array Transceiver Front-End With Hybrid Architecture Phase Shifters and Gain Controllers

B. Chi, Haikun Jia, W. Deng, 2023, IEEE Transactions on Microwave Theory and Techniques.

A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS

B. Chi, Haikun Jia, W. Deng, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique

Kenichi Okada, Akira Matsuzawa, Teerachot Siriburanon, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

Kenichi Okada, Hanli Liu, Akira Matsuzawa, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Time Multiplexed Beam-Forming with Space-Frequency Transformation

A.H.M. van Roermund, Reza Mahmoudi, Wei Deng, 2012 .

A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation

Kenichi Okada, Akira Matsuzawa, Wei Deng, 2010, 2010 IEEE Asian Solid-State Circuits Conference.