Subodh Kumar Singhal

Scalable architectures for VLSI implementation of DSP algorithms

Subodh Kumar Singhal, 2017 .

Design of 1.5 GHz Quasilumped Microstrip Highpass Filter

Subodh Kumar Singhal, Deepak Sharma, Ram Mehar Singh Dhariwal, 2009, 2009 First International Conference on Computational Intelligence, Communication Systems and Networks.

Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform

Basant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Area-delay and energy efficient multi-operand binary tree adder

Subodh Kumar Singhal, Sujit Kumar Patel, 2020, IET Circuits Devices Syst..

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

M. N. Shanmukha Swamy, Basant K. Mohanty, Pramod Kumar Meher, 2016, Integr..

Design of 1.3 GHz Microstrip Highpass Filter Using Optimum Distributed Short Circuited Stubs

Subodh Kumar Singhal, Deepak Sharma, Ram Mehar Singh Dhariwal, 2009, 2009 First International Conference on Computational Intelligence, Communication Systems and Networks.

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic

Basant Kumar Mohanty, Subodh Kumar Singhal, B. K. Mohanty, 2016, J. Circuits Syst. Comput..

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder

Gaurav Saxena, Basant Kumar Mohanty, Subodh Kumar Singhal, 2020, J. Circuits Syst. Comput..

Challenges for Underwater Instrumentation

Subodh Kumar Singhal, 2009 .

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer

Basant K. Mohanty, Subodh Kumar Singhal, 2016, Circuits Syst. Signal Process..