K. Tamaru

发表

Step by step placement strategies for building block layout

H. Onodera, Mamoru Sakamoto, T. Kurihara, 1989, IEEE International Symposium on Circuits and Systems,.

A novel mode of write operation utilizing avalanche-tunnel injection in MNOS memory transistor

Y. Nishi, I. Nojima, Yukimasa Uchida, 1972 .

Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)

Kenichi Okada, Hidetoshi Onodera, Keikichi Tamaru, 1999 .

A method for improving reusability of design procedures of analog circuits—storage and reuse of design constraints and uncertain parameters

Hidetoshi Onodera, Takashi Morie, Keikichi Tamaru, 2000 .

Physical insights on imprint and application to functional memory with ferroelectric materials

Kazutoshi Kobayashi, K. Tamaru, H. Nozawa, 2001 .

Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation

Takashi Morie, Hidetoshi Onodera, Keikichi Tamaru, 1995 .

Operational amplifier compilation with performance optimization

Hidetoshi Onodera, Keikichi Tamaru, Hiroyuki Kanbara, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPP

Kazutoshi Kobayashi, Hidetoshi Onodera, Keikichi Tamaru, 1998 .

Verity - A formal verification program for custom CMOS circuits

Arvind Srinivasan, David P. LaPotin, Andreas Kuehlmann, 1995, IBM J. Res. Dev..

Estimation of short-Circuit Power Dissipation for Static CMOS Gates

Hidetoshi Onodera, Keikichi Tamaru, Akio Hirata, 1996 .

A scheduling algorithm for synthesis of bus-partitioned architectures

K. Tamaru, V. Moshnyaga, F. Ohbayashi, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

A new architecture for in-memory image convolution

Kazuhiro Suzuki, Keikichi Tamaru, Vasily G. Moshnyaga, 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

Operational-amplifier compilation with performance optimization

Hidetoshi Onodera, Keikichi Tamaru, Hiroyuki Kanbara, 1990 .

Flexible LSI Devices : FPGA ( Flexible Hardware)

Keikichi Tamaru, K. Tamaru, 1999 .

Branch-and-bound placement for building block layout

Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru, 1991, 28th ACM/IEEE Design Automation Conference.

High speed merged multiplication

Keikichi Tamaru, Farhad Fuad Islam, K. Tamaru, 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

The Trend of Functional Memory Development (Special Issue on LSI Memories)

Keikichi Tamaru, K. Tamaru, 1993 .

System design of a special-purpose computer for LSI design rule checking

Hidetoshi Onodera, Keikichi Tamaru, H. Onodera, 1987, Systems and Computers in Japan.

Energy saving techniques for architecture design of portable embedded devices

Keikichi Tamaru, Vasily G. Moshnyaga, K. Tamaru, 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

Proposal of a timing model for CMOS logic gates driving a CRC /spl pi/ load

H. Onodera, A. Hirata, K. Tamaru, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).