Naveena Nagi

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A comprehensive test framework for analog and mixed-signal circuits

Naveena Nagi, 1995 .

Hierarchical fault modeling for linear analog circuits

Jacob A. Abraham, Naveena Nagi, 1996 .

Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling

Abhijit Chatterjee, Pramodchandran N. Variyam, Naveena Nagi, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

DRAFTS: Discretized Analog Circuit Fault Simulator

Abhijit Chatterjee, Jacob A. Abraham, Naveena Nagi, 1993, 30th ACM/IEEE Design Automation Conference.

Delay fault testing of iterative arithmetic arrays

Abhijit Chatterjee, Rabindra K. Roy, Naveena Nagi, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Test metrics for analog parametric faults

Stephen K. Sunter, Naveena Nagi, S. Sunter, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Simplified polynomial-fitting algorithm for DAC and ADC bist

Naveena Nagi, Stephen Sunter, 1999 .

Hierarchical fault modeling for analog and mixed-signal circuits

Jacob A. Abraham, Naveena Nagi, J. Abraham, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

MIXER: Mixed-signal fault simulator

Abhijit Chatterjee, Jacob A. Abraham, Naveena Nagi, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Design for testability and built-in self-test of mixed-signal circuits: a tutorial

Abhijit Chatterjee, Naveena Nagi, A. Chatterjee, 1997, Proceedings Tenth International Conference on VLSI Design.

Low-cost DC built-in self-test of linear analog circuits using checksums

Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi, 1996, Proceedings of 9th International Conference on VLSI Design.

W-COST DC BUILT-IN SELF-TEST OF LINEAR ANALOG C USING CHECKSUMS

Abhijit Chatterjee, Naveena Nagi, Bruce Kim, 1996 .

A simplified polynomial-fitting algorithm for DAC and ADC BIST

Stephen K. Sunter, Naveena Nagi, 1997, Proceedings International Test Conference 1997.

Hierarchical statistical inference model for specification based testing of analog circuits

Abhijit Chatterjee, Pramodchandran N. Variyam, Naveena Nagi, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Fault-based automatic test generator for linear analog circuits

Abhijit Chatterjee, Jacob A. Abraham, Ashok Balivada, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

A unified approach for fault simulation of linear mixed-signal circuits

Abhijit Chatterjee, Jacob A. Abraham, Hong Zheng, 1996, J. Electron. Test..

DC Built-In Self-Test for Linear Analog Circuits

Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi, 1996, IEEE Des. Test Comput..

Fault simulation of linear analog circuits

Abhijit Chatterjee, Jacob A. Abraham, Naveena Nagi, 1993, J. Electron. Test..

Signature analysis for analog and mixed-signal circuit test response compaction

Abhijit Chatterjee, Jacob A. Abraham, Naveena Nagi, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault-based automatic test generator for linear analog circuits

Abhijit Chatterjee, Jacob A. Abraham, Ashok Balivada, 1993, ICCAD.

A signature analyzer for analog and mixed-signal circuits

Abhijit Chatterjee, Jacob A. Abraham, Naveena Nagi, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Efficient multisine testing of analog circuits

Abhijit Chatterjee, Jacob A. Abraham, Ashok Balivada, 1995, Proceedings of the 8th International Conference on VLSI Design.

Fault simulation of linear analog circuits

Abhijit Chatterjee, Jacob A. Abraham, Naveena Nagi, 1993 .