I. Voyiatzis

发表

C. Efstathiou, I. Voyiatzis, S. Hamdioui, 2012, 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

A novel architecture to reduce test time in march-based SRAM tests

C. Efstathiou, I. Voyiatzis, C. Sgouropoulou, 2012, 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

An efficient architecture for accumulator-based test generation of SIC pairs

Costas Efstathiou, I. Voyiatzis, 2008, DTIS 2008.

Two-pattern generation based on accumulators with 1's complement adders

I. Voyiatzis, C. Efstathiou, C. Efstathiou, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Proceedings of the 21st Pan-Hellenic Conference on Informatics

Cleo Sgouropoulou, Christos Douligeris, Ilias K. Savvas, 2017, PCI.

Decoder-based Decompression for test sets containing don’t cares

I. Voyiatzis, H. Antonopoulou, 2007, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Output response compaction in RAS-based schemes

C. Efstathiou, I. Voyiatzis, H. Antonopoulou, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

Algorithm for the generation of SIC pairs and its implementation in a BIST environment

Constantin Halatsis, I. Voyiatzis, Th. Haniotakis, 2006 .

A Low-Cost Optimal Time SIC Pair Generator

Costas Efstathiou, I. Voyiatzis, H. Antonopoulou, 2010 .

Reliability considerations in mobile devices

I. Voyiatzis, S. Sinitos, H. Antonopoulou, 2007, Mobimedia 2007.

A concurrent BIST architecture based on Monitoring Square Windows

C. Efstathiou, I. Voyiatzis, Th. Haniotakis, 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Accumulator-based built-in self-test generator for robustly detectable sequential fault testing

Constantin Halatsis, Dimitris Gizopoulos, I. Voyiatzis, 2004 .

Low-overhead two-dimensional test pattern generation

C. Efstathiou, I. Voyiatzis, H. Antonopoulou, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

On reducing aliasing in accumulator-based compaction

I. Voyiatzis, 2008, 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era.

Accumulator - based compression in symmetric transparent RAM BIST

I. Voyiatzis, I. Voyiatzis, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

On the modulo 2n+1 multiplication for diminished-1 operands

C. Efstathiou, I. Voyiatzis, N. Sklavos, 2008, 2008 2nd International Conference on Signals, Circuits and Systems.

On the diminished-1 modulo 2N+1 fused multiply-add units

C. Efstathiou, I. Voyiatzis, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).