Beomsup Kim

发表

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

Ook Kim, Chanhong Park, Beomsup Kim, 2001, IEEE J. Solid State Circuits.

A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

Kwyro Lee, Beomsup Kim, Seog-Jun Lee, 1997, IEEE J. Solid State Circuits.

A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS

Beomsup Kim, Chan-Hong Park, Chanhong Park, 1999 .

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

Beomsup Kim, Yongchul Song, Beomsup Kim, 2004, IEEE J. Solid State Circuits.

Rejection G m C Filter with In-Situ Calibration for Use in Transmitter Applications

Jacques C. Rudell, Beomsup Kim, Ozan E. Erdogan, 2005 .

A digital audio signal processor for cellular phone application

Chanhong Park, Beomsup Kim, Jeongsik Yang, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

A digital phase-locked loop with variable loop gains derived from RLS method

Seung Hee Choi, Beomsup Kim, Byungjin Chun, 1997, Proceedings of ICC'97 - International Conference on Communications.

Analysis of timing jitter in CMOS ring oscillators

Beomsup Kim, Paul R. Gray, Todd C. Weigandt, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

A low-noise fast-lock phase-locked loop with adaptive bandwidth control

Beomsup Kim, Joonsuk Lee, Beomsup Kim, 2000, IEEE Journal of Solid-State Circuits.

Quadrature direct digital frequency synthesizers using interpolation-based angle rotation

Beomsup Kim, Yongchul Song, Beomsup Kim, 2004, IEEE Trans. Very Large Scale Integr. Syst..

A 5–GHz band I/Q clock generator using a self–calibration technique

Hyung Ki Ahn, Joonho Gil, Beomsup Kim, 2002 .

A low-noise, 900-MHz VCO in 0.6-μm CMOS

Beomsup Kim, Chan-Hong Park, 1999, IEEE J. Solid State Circuits.

Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two

Dong Sam Ha, Shen Wang, Beomsup Kim, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

C.S.G. Conroy, Jinwook Kim, Jeongsik Yang, 2005, IEEE Journal of Solid-State Circuits.

A 192MHz differential XO based frequency quadrupler with sub-picosecond jitter in 28nm CMOS

Michael P. Flynn, Beomsup Kim, Yashar Rajavi, 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS

Michael P. Flynn, Beomsup Kim, Yashar Rajavi, 2017, IEEE Journal of Solid-State Circuits.

A low-noise phase-locked loop design by loop bandwidth optimization

Kyoohyun Lim, Beomsup Kim, Chan-Hong Park, 2000, IEEE Journal of Solid-State Circuits.

A low-noise 900 MHz VCO in 0.6 /spl mu/m CMOS

Beomsup Kim, Chan-Hong Park, Beomsup Kim, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

PLL/DLL system noise analysis for low jitter clock synthesizer design

Beomsup Kim, Paul R. Gray, Todd C. Weigandt, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

Hyoungsik Nam, Hyun-Jun Yoon, Churoo Park, 1998, IEEE J. Solid State Circuits.

Design of a 3.0 V CMOS continuous time low-pass filter with on-chip tuning circuits for CDMA cellular phone application

Beomsup Kim, Chan-Hong Park, Beomsup Kim, 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.