G. Curello

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

J. Rizk, K. Soumyanath, P. VanDerVoorn, 2010, 2010 Symposium on VLSI Technology.

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

M. Agostinelli, G. Curello, H. Deshpande, 2011, 2011 International Reliability Physics Symposium.

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

G. Curello, W. Hafez, M. Kang, 2012, 2012 International Electron Devices Meeting.

A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

S. Natarajan, B. Holt, J. Neirynck, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..