K. Phoa

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

J. Rizk, K. Soumyanath, P. VanDerVoorn, 2010, 2010 Symposium on VLSI Technology.

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

M. Agostinelli, G. Curello, H. Deshpande, 2011, 2011 International Reliability Physics Symposium.

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

G. Curello, W. Hafez, M. Kang, 2012, 2012 International Electron Devices Meeting.

A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

S.-J. Choi, W. Hafez, M. Kang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

J. Lee, K. Komeyli, K. Phoa, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Transistor reliability characterization and modeling of the 22FFL FinFET technology

S. Liu, L. Jiang, K. Phoa, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications

S. Mudanai, K. Phoa, P. Bai, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Intel 22nm FinFET (22FFL) Process Technology for RF and mm Wave Applications and Circuit Design Optimization for FinFET Technology

K. Phoa, B. Sell, S. Ravikumar, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).