J. Xu

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

J. Rizk, K. Soumyanath, P. VanDerVoorn, 2010, 2010 Symposium on VLSI Technology.

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

M. Agostinelli, G. Curello, H. Deshpande, 2011, 2011 International Reliability Physics Symposium.

Die-package stress interaction impact on transistor performance

J. Xu, J. Hicks, D. Pantuso, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Erratic fluctuations of sram cache vmin at the 90nm process technology node

J. Jopling, M. Jones, M. Agostinelli, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..