N. Ranganathan

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Design of a comparator tree based on reversible logic

H. Thapliyal, N. Ranganathan, R. Ferreira, 2010, 10th IEEE International Conference on Nanotechnology.

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks

S. Bhanja, N. Ranganathan, K. Lingasubramanian, 2004 .

A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera ( S 2 DC ) Design

S. Mohanty, N. Ranganathan, R. Namballa, 2005 .

A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera ( S 2 DC ) Design

S. Mohanty, N. Ranganathan, R. Namballa, 2005 .

Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate

N. Ranganathan, Himanshu Thapliyal, H. Thapliyal, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Foreword for March 1996 issue

Chun Wong, Francky Catthoor, Dw Bouldin, 1996 .

A novel optimization method for reversible logic circuit minimization

N. Ranganathan, Matthew Morrison, N. Ranganathan, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Radu Marculescu, Majid Sarrafzadeh, Vishwani D. Agrawal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits

H. Thapliyal, N. Ranganathan, S. Kotiyal, 2014, Field-Coupled Nanocomputing.

A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets

N. Ranganathan, Upavan Gupta, N. Ranganathan, 2010, IEEE Transactions on Knowledge and Data Engineering.

A microeconomic approach to multi-objective spatial clustering

N. Ranganathan, Upavan Gupta, N. Ranganathan, 2008, 2008 19th International Conference on Pattern Recognition.

A microeconomic approach to multi-robot team formation

N. Ranganathan, Upavan Gupta, N. Ranganathan, 2007, 2007 IEEE/RSJ International Conference on Intelligent Robots and Systems.

CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL

N. Ranganathan, Ravi Namballa, Narender Hanchate, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Game theoretic modeling of voltage and frequency scaling during behavioral synthesis

N. Ranganathan, Ashok K. Murugavel, N. Ranganathan, 2004, 17th International Conference on VLSI Design. Proceedings..

Gate sizing and buffer insertion using economic models for power optimization

N. Ranganathan, Ashok K. Murugavel, N. Ranganathan, 2004, 17th International Conference on VLSI Design. Proceedings..

Efficient computation of gabor filter based multiresolution responses

N. Ranganathan, Kamesh Namuduri, Rajiv Mehrotra, 1994, Pattern Recognit..

A CMOS VLSI Chip for Motion Detection

N. Ranganathan, Rajiv Mehrotra, S. Kurji, 1992, The Fifth International Conference on VLSI Design.

A VLSI architecture for dynamic scene analysis

N. Ranganathan, Rajiv Mehrotra, R. Mehrotra, 1991, CVGIP Image Underst..

A VLSI system for difference picture-based motion analysis

N. Ranganathan, R. Mehrotra, R. Mehrotra, 1989, [Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence.

Gabor filter-based edge detection

N. Ranganathan, Kamesh Namuduri, Rajiv Mehrotra, 1992, Pattern Recognit..

Least-square estimation of average power in digital CMOS circuits

Ramamurti Chandramouli, N. Ranganathan, Ashok K. Murugavel, 2002, IEEE Trans. Very Large Scale Integr. Syst..

An expected-utility based approach to variation aware VLSI optimization under scarce information

N. Ranganathan, Upavan Gupta, N. Ranganathan, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Mach-Zehnder interferometer based design of all optical reversible binary adder

N. Ranganathan, Himanshu Thapliyal, Saurabh Kotiyal, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Two-dimensional Systolic Array Processor for Image Processing

N. Ranganathan, Patrick McCabe, Minesh I. Patel, 1992, The Fifth International Conference on VLSI Design.

Efficient VLSI designs for data transformation of tree-based codes

Mostafa A. Bassiouni, Amar Mukherjee, Nagarajan Ranganathan, 1991 .

A tree matching chip

Abdel Ejnioui, N. Ranganathan, Vamsi Krishna, 1996, Proceedings of 9th International Conference on VLSI Design.

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard

Nagarajan Ranganathan, M. Kovac, N. Ranganathan, 1995, Proc. IEEE.

MARVLE: a VLSI chip for data compression using tree-based codes

Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits

N. Ranganathan, Matthew Morrison, Jay Ligatti, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reversible Logic-Based Concurrently Testable Latches for Molecular QCA

N. Ranganathan, H. Thapliyal, H. Thapliyal, 2010, IEEE Transactions on Nanotechnology.

A VLSI architecture for a half-edge-based corner detector

N. Ranganathan, Rajiv Mehrotra, Sanjay Nichani, 1991, Machine Vision and Applications.

Corner detection

N. Ranganathan, Rajiv Mehrotra, Sanjay Nichani, 1990, Pattern Recognit..

Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory

N. Ranganathan, Narender Hanchate, N. Ranganathan, 2006, IEEE Transactions on Computers.

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs

N. Ranganathan, Himanshu Thapliyal, H. Thapliyal, 2010, JETC.

A game-theoretic approach for binding in behavioral synthesis

N. Ranganathan, Ashok K. Murugavel, N. Ranganathan, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

C/sup 3/L: a chip for connected component labeling

N. Ranganathan, Ashley Rasquinha, N. Ranganathan, 1997, Proceedings Tenth International Conference on VLSI Design.

A high speed systolic architecture for labeling connected components in an image

N. Ranganathan, Rajiv Mehrotra, S. Subramaniam, 1991, Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing.

Cascaded Bayesian inferencing for switching activity estimation with correlated inputs

Sanjukta Bhanja, N. Ranganathan, S. Bhanja, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Mapping and parallel implementation of Bayesian belief networks

Sudeep Sarkar, N. Ranganathan, Nina Saxena, 1996, Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing.

Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up-counter

Matthew Morrison, Nagarajan Ranganathan, N. Ranganathan, 2011, 2011 11th IEEE International Conference on Nanotechnology.

ILP models for simultaneous energy and transient power minimization during behavioral synthesis

Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi, 2006, TODE.

An intelligent system for failure detection and control in an autonomous underwater vehicle

N. Ranganathan, Minesh I. Patel, R. Sathyamurthy, 2001, IEEE Trans. Syst. Man Cybern. Part A.

High-speed VLSI designs for Lempel-Ziv-based data compression

Nagarajan Ranganathan, S. Henriques, N. Ranganathan, 1993 .

An Efficient VLSI Architecture for Template Matching

N. Ranganathan, Satish Venugopal, 1994, 1994 International Conference on Parallel Processing Vol. 1.

New cost metrics for iterative task assignment algorithms in heterogeneous computing systems

N. Ranganathan, Raju D. Venkataramana, N. Ranganathan, 2000, Proceedings 9th Heterogeneous Computing Workshop (HCW 2000) (Cat. No.PR00556).

Multiple cost optimization for task assignment in heterogeneous computing systems using learning automata

N. Ranganathan, Raju D. Venkataramana, N. Ranganathan, 1999, Proceedings. Eighth Heterogeneous Computing Workshop (HCW'99).

A game theoretic approach for power optimization during behavioral synthesis

N. Ranganathan, Ashok K. Murugavel, N. Ranganathan, 2003, IEEE Trans. Very Large Scale Integr. Syst..

CREAM: combined register and module assignment with floorplanning for low power datapath synthesis

Vamsi K. Srikantam, N. Ranganathan, Srikanth T. Srinivasan, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

SAP: design of a systolic array processor for computation in vision

N. Ranganathan, Sanjay Nichani, N. Ranganathan, 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Variation-aware multimetric optimization during gate sizing

N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam, 2009, TODE.

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty

N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam, 2008, GLSVLSI '08.

Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition

V. Mahalingam, Nagarajan Ranganathan, N. Ranganathan, 2006, IEEE Transactions on Computers.

Switching activity estimation of VLSI circuits using Bayesian networks

Sanjukta Bhanja, N. Ranganathan, S. Bhanja, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Social Fairness in Multi-Emergency Resource Management

N. Ranganathan, Upavan Gupta, N. Ranganathan, 2006, 2006 IEEE International Symposium on Technology and Society.

Reversible logic based multiplication computing unit using binary tree data structure

H. Thapliyal, N. Ranganathan, S. Kotiyal, 2015, The Journal of Supercomputing.

Efficient reversible NOR gates and their mapping in optical computing domain

N. Ranganathan, Himanshu Thapliyal, Saurabh Kotiyal, 2014, Microelectron. J..

Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits

N. Ranganathan, Himanshu Thapliyal, Saurabh Kotiyal, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies

N. Ranganathan, Himanshu Thapliyal, H. Thapliyal, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

A new design of the reversible subtractor circuit

Himanshu Thapliyal, Nagarajan Ranganathan, H. Thapliyal, 2011, 2011 11th IEEE International Conference on Nanotechnology.

Design of efficient reversible logic-based binary and BCD adder circuits

N. Ranganathan, Himanshu Thapliyal, H. Thapliyal, 2013, JETC.

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate

N. Ranganathan, Himanshu Thapliyal, H. Thapliyal, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

LECTOR: a technique for leakage reduction in CMOS circuits

N. Ranganathan, Narender Hanchate, N. Ranganathan, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications

N. Ranganathan, Matthew Morrison, N. Ranganathan, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design of static and dynamic RAM arrays using a novel reversible logic gate and decoder

Matthew Morrison, Nagarajan Ranganathan, Matthew Lewandowski, 2011, 2011 11th IEEE International Conference on Nanotechnology.

A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors

N. Ranganathan, Narender Hanchate, N. Ranganathan, 2004, 17th International Conference on VLSI Design. Proceedings..

SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm

Mario Kovac, N. Ranganathan, M. Varanasi, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Systolic VLSI implementations of a Galois field arithmetic algorithms

N. Ranganathan, M. Kovac, N. Ranganathan, 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division

N. Ranganathan, Mario Kovac, M. Varanasi, 1993, The Sixth International Conference on VLSI Design.

A systolic algorithm and architecture for Galois field arithmetic

N. Ranganathan, Mario Kovac, M. Varanasi, 1992, Proceedings Sixth International Parallel Processing Symposium.

A Cache Coherence Protocol for the BidirectionalRing Based MultiprocessorHitoshi OiDept

N. Ranganathan, Hitoshi Oi, 1999 .

An efficient and accurate logarithmic multiplier based on operand decomposition

N. Ranganathan, Venkataraman Mahalingam, N. Ranganathan, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

A new reversible design of BCD adder

N. Ranganathan, Himanshu Thapliyal, H. Thapliyal, 2011, 2011 Design, Automation & Test in Europe.

A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization

N. Ranganathan, Ashok K. Murugavel, N. Ranganathan, 2003, Proceedings 21st International Conference on Computer Design.

Another Step in the Right Direction for TVLSI

Nagarajan Ranganathan, N. Ranganathan, 2004 .

A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations

N. Ranganathan, Koustav Bhattacharya, N. Ranganathan, 2009, 2009 10th International Symposium on Quality Electronic Design.

VLSI algorithms for data compression

Mostafa A. Bassiouni, Amar Mukherjee, Nagarajan Ranganathan, 1991 .

Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain

N. Ranganathan, Himanshu Thapliyal, Saurabh Kotiyal, 2014, Trans. Comput. Sci..

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

N. Ranganathan, Venkataraman Mahalingam, J. E. Harlow, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Novel Approach for Variation Aware Power Minimization during Gate Sizing

N. Ranganathan, Venkataraman Mahalingam, Justin E. Harlow, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

A VLSI system architecture for optical flow computation

N. Ranganathan, Koustav Bhattacharya, Venkataraman Mahalingam, 2009, 2009 IEEE International Symposium on Circuits and Systems.

SMAC: A VLSI Architecture for Scene Matching

Raghu Sastry, R. Venkatesan, N. Ranganathan, 1998, Real Time Imaging.

A VLSI architecture for computing the optimal correspondence of string subsequences

N. Ranganathan, R. Motamarri, N. Ranganathan, 1997, Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97.

Design partitioning on single-chip emulation systems

Abdel Ejnioui, N. Ranganathan, A. Ejnioui, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Adaptive VBR video traffic management for higher utilization of ATM networks

Girish Chiruvolu, N. Ranganathan, Ravi Sankar, 1998, CCRV.

A scene-based generalized Markov chain model for VBR video traffic

Tapas K. Das, Ravi Sankar, Nagarajan Ranganathan, 1998, ICC '98. 1998 IEEE International Conference on Communications. Conference Record. Affiliated with SUPERCOMM'98 (Cat. No.98CH36220).

A VLSI architecture for computing the tree-to-tree distance

Raghu Sastry, N. Ranganathan, N. Ranganathan, 1995, Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.

A new CRL gate as super class of Fredkin gate to design reversible quantum circuits

Himanshu Thapliyal, Nagarajan Ranganathan, Apeksha Bhatt, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).