A. Dasu

发表

Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA

Thomas E. Sarvey, M. Bakir, Yang Zhang, 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

A Framework for the Design of the Heterogeneous Hierarchical Routing Architecture of a Dynamically Reconfigurable Application Specific Media Processor

S. Panchanathan, A. Akoglu, A. Dasu, 2003 .

Package-Level Integration of Liquid Cooling Technology with Microchannel IHS for High Power Cooling

R. Mongia, R. Mahajan, D. Kulkarni, 2021, 2021 20th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm).

A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA

Aravind Dasu, Pedro C. Diniz, Vanderlei Bonato, 2018, J. Signal Process. Syst..

FlexScore: Quantifying Flexibility

Aravind Dasu, Martin Langhammer, Eriko Nurvitadhi, 2021, IEEE Computer Architecture Letters.

Automatic Compiler Based FPGA Accelerator for CNN Training

Eriko Nurvitadhi, Jae-sun Seo, Yu Cao, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

Analysis of Power Delivery Network (PDN) in Bridge-Chips for 2.5-D Heterogeneous Integration

M. Bakir, E. Nurvitadhi, M. Pant, 2022, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Microfluidic Cooling of a 14-nm 2.5-D FPGA With 3-D Printed Manifolds for High-Density Computing: Design Considerations, Fabrication, and Electrical Characterization

Thomas E. Sarvey, Sreejith Kochupurackal Rajan, M. Bakir, 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.

SCALE ROBUST HEAD POSE ESTIMATION BASED ON RELATIVE HOMOGRAPHY TRANSFORMATION

Aravind Dasu, Heng-Da Cheng, Chenguang Liu, 2014 .

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory

Eriko Nurvitadhi, Shihui Yin, Shreyas K. Venkataramanaiah, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs

Gregory K. Chen, Ram Krishnamurthy, Aravind Dasu, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Review of Literature on Terminal Box Control, Occupancy Sensing Technology and Multi-zone Demand Control Ventilation (DCV)

Jian Zhang, Guopeng Liu, Aravind R. Dasu, 2012 .

Design of embedded compute-intensive processing elements and their scheduling in a reconfigurable environment

S. Panchanathan, A. Sudarsanam, A. Dasu, 2005, Canadian Journal of Electrical and Computer Engineering.

Cluster Extraction for Hybrid FPGA Architecture in Computation Intensive Applications

Ali Akoglu, Aravind Dasu, Sethuraman Panchanathan, 2004, International Conference on Engineering of Reconfigurable Systems and Algorithms.

Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures

Aravind Dasu, Arvind Sudarsanam, Sethuraman Panchanathan, 2004, International Conference on Engineering of Reconfigurable Systems and Algorithms.

PRR-PRR Dynamic Relocation

Aravind Dasu, Arvind Sudarsanam, Ramachandra Kallam, 2009, IEEE Computer Architecture Letters.

IP Cores for Graph Kernels on FPGAs

Viktor K. Prasanna, Rajgopal Kannan, Sanmukh R. Kuppannagari, 2019, 2019 IEEE High Performance Extreme Computing Conference (HPEC).

A c to register transfer level algorithm using structured circuit templates: a case study with simulated annealing

Aravind Dasu, Jonathan D. Phillips, A. Dasu, 2008 .

Complexity analysis of sprites in MPEG-4

Sethuraman Panchanathan, Raghavendra C. Nagaraj, Aravind R. Dasu, 2001, IS&T/SPIE Electronic Imaging.

A Power Efficient Linear Equation Solver on A Multi-Fpgaaccelerator

Aravind Dasu, Arvind Sudarsanam, Seth Young, 2010 .