Anu Gupta

发表

Design and performance evaluation of a low transistor ternary CNTFET SRAM cell

Sneh Lata Murotiya, Pramod Srinivasan, Anirudha Bhat, 2015, 2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV).

Performance evaluation of CNTFET based Dynamic Ternary Content Addressable Memory cell

Sneh Lata Murotiya, Anu Gupta, 2013, 2013 Annual IEEE India Conference (INDICON).

Design of High Resolution, Fast Locking, Low Power Multiphase-Output Delay Locked Loop

Anu Gupta, Nirmalya Sanyal, Suman Kumar Panda, 2011 .

Leakage Immune 9T-SRAM Cell in Sub-threshold Region

Abhijit R. Asati, Anu Gupta, Priya Gupta, 2016 .

A Novel Ultra Low Power , High Impedance Current Mirror Circuit for Biasing Operational Amplifier in Subthreshold Region

Anu Gupta, Rajeev Dua, 2013 .

Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime

Abhijit R. Asati, Anu Gupta, Priya Gupta, 2016 .

On-Chip Intelligent Dynamic Frequency Scaling for Real-Time Systems

Prachi Sharma, Anu Gupta, Arkid Bera, 2020 .

Study the Temperature-Dependent Analytical Time Domain Delay Model for Performance Optimization of Single-Walled Carbon Nanotube (SWCNT) Bundle Based VLSI Interconnects

M. Rai, Anu Gupta, 2016 .

Energy Efficient Hardware Implementation of 2-D Convolution for Convolutional Neural Network

K. Raju, Anu Gupta, Shashi Kant Sharma, 2022, 2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON).

Graphene nanoribbon based static random access memory for better noise margin and power reduction

Anu Gupta, Abhishek Gune, Anu Gupta, 2013, International Conference on Advanced Nanomaterials & Emerging Engineering Technologies.

Designing of Graphene Nanoribbon based Static Random Access Memory

Anu Gupta, Abhishek Gune, 2013 .

Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

Anu Gupta, Abhijit R. Asati, Vineet Kumar, 2018, IET Image Process..

Hardware Accelerators for Iris Localization

Abhijit R. Asati, Anu Gupta, Vineet Kumar, 2017, Journal of Signal Processing Systems.

Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images

Abhijit R. Asati, Vineet Kumar, Abhijit Asati, 2016 .

Design of content-addressable memory cell using CNTFETs

Sneh Lata Murotiya, Anu Gupta, Anu Gupta, 2015 .

Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs

Anu Gupta, Sneh Lata Murotiya, Anu Gupta, 2015, 2015 28th International Conference on VLSI Design.

CNTFET-based design of dynamic ternary full adder cell

Anu Gupta, Sneh Lata Murotiya, Sparsh Vasishth, 2014, 2014 Annual IEEE India Conference (INDICON).

A Novel Design of Ternary Full Adder Using CNTFETs

Sneh Lata Murotiya, Anu Gupta, 2014, Arabian Journal for Science and Engineering.

A Novel Design of Ternary Full Adder Using CNTFETs

Anu Gupta, Sneh Lata Murotiya, Anu Gupta, 2014, Arabian Journal for Science and Engineering.

Low-latency median filter core for hardware implementation of 5 × 5 median filtering

Anu Gupta, Abhijit R. Asati, Vineet Kumar, 2017, IET Image Process..

Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm

Anu Gupta, Abhijit R. Asati, Priya Gupta, 2018 .

Comparative Analysis of Phase/Frequency Detector in a Complete PLL System

C. Shekhar, Anu Gupta, Buddhi Prakash Sharma, 2023, 2023 International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE).

Low Power Cascaded Three Stage Amplifier with Multipath Nested Miller Compensation

Nitin Chaturvedi, Anu Gupta, Maneesh Menon, 2010, 2010 International Conference on Recent Trends in Information, Telecommunication and Computing.

Novel design of ternary magnitude comparator using CNTFETs

Anu Gupta, Sneh Lata Murotiya, Sparsh Vasishth, 2014, 2014 Annual IEEE India Conference (INDICON).

A Novel Redundant Binary Number to Natural Binary Number Converter

Chandra Shekhar, Subhendu Kumar Sahoo, Anu Gupta, 2010, J. Signal Process. Syst..

Dual channel addition based FFT processor architecture for signal and image processing

Chandra Shekhar, Subhendu Kumar Sahoo, Anu Gupta, 2009, Int. J. High Perform. Syst. Archit..

Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders

Anu Gupta, Chandra Shekhar, C. Shekhar, 2005 .

Automation of clock distribution network design for digital integrated circuits using divide and conquer technique

Anu Gupta, Bipin Kulkarni, Anu Gupta, 2006, Integr..

Hardware Implementation of a Biometric Fingerprint Identification System with Embedded Matlab

Nitin Chaturvedi, Anu Gupta, Jithin P. Thomas, 2010, 2010 International Conference on Advances in Recent Technologies in Communication and Computing.

A novel hardware efficient Digital Neural Network architecture implemented in 130nm technology

Cherin Joseph, Anu Gupta, Anu Gupta, 2010, 2010 The 2nd International Conference on Computer and Automation Engineering (ICCAE).

CNTFET-based low power design of 4-input ternary XOR function

Anu Gupta, Sneh Lata Murotiya, Ayan Pandit, 2014, 2014 International Conference on Computer and Communication Technology (ICCCT).

Studying Crosstalk Trends for Signal Integrity on Interconnects using Finite Element Modeling

Anu Gupta, J. S. Grover, Jaskaran Singh Grover, 2013 .

Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology

Pramod Kumar, Anu Gupta, Sachin Maheshwari, 2013, VDAT.

Dedicated hardware architecture for localizing iris in VW images

Vineet Kumar, Anu Gupta, Abhijit R. Asati, 2020, J. King Saud Univ. Comput. Inf. Sci..

Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images

Abhijit R. Asati, Vineet Kumar, Abhijit Asati, 2017 .

A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images

Anu Gupta, Abhijit R. Asati, Vineet Kumar, 2016, J. Electr. Comput. Eng..

A Review on Ultra Low Power Design Technique: Subthreshold Logic

Anu Gupta, Abhijit R. Asati, Priya Gupta, 2013 .

An Iris localization method for noisy infrared iris images

Anu Gupta, Abhijit R. Asati, Vineet Kumar, 2015, 2015 IEEE International Conference on Signal and Image Processing Applications (ICSIPA).

Iris localization based on integro-differential operator for unconstrained infrared iris images

Vineet Kumar, Anu Gupta, Abhijit R. Asati, 2015, 2015 International Conference on Signal Processing, Computing and Control (ISPCC).