J. Chou

Optimum halo structure for sub-0.1 /spl mu/m CMOSFETs

W. Yeh, J. Chou, 2001 .

A novel 0.25 /spl mu/m shallow trench isolation technology

S.W. Sun, W. Lur, S. Sun, 1996, International Electron Devices Meeting. Technical Digest.

MgO/Cu2O Superlattices: Growth of Epitaxial Two-Dimensional Nanostructures

Q. Y. Chen, L. Tu, N. Ho, 2016, Journal of Electronic Materials.

Interface trap effect on gate induced drain leakage current in submicron N-MOSFET's

C. Y. Chang, Chimoon Huang, Tahui Wang, 1994 .

A Capacitance Ratio Method Used for Leff Extraction of an Advanced Metal-Oxide-Semiconductor Device with Halo Implant

Ying-Cong Chen, J. Chou, Heng-Sheng Huang, 2001 .

A Modified Capacitance–Voltage Method Used for Leff Extraction and Process Monitoring in Advanced 0.15 µm Complementary Metal-Oxide-Semiconductor Technology and Beyond

J. Chou, Heng-Sheng Huang, G. Hong, 2001 .