S. Filipiak

Avoiding plasma induced damage to gate oxide with conductive top film (CTF) on PECVD contact etch stop layer

L. Kang, M. Turner, S. Song, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Multi-Layer Model for Stressor Film Deposition

D. Tekleab, V. Kolagunta, B. Winstead, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization

S. Das, T. Lii, M. Angyal, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Integration of Multi-Level Copper Metallization into a High Performance Sub-0.25μM Technology

M. Angyal, Ajay Jain, V. Kaushik, 1998 .

Theoretical and experimental analysis of the low dielectric constant of fluorinated silica

M. Angyal, A. Demkov, S. Zollner, 1999 .

Integration Challenges of Inorganic Low-K (K≤2.5) Materials with Cu for Sub-0.25µm Multilevel Interconnects

J. Wetzel, J. K. Watanabe, C. Hobbs, 1999 .

Integration Of BPDA-PDA Polyimide With Two Levels Of Al(Cu) Interconnects

J. Wetzel, B. Nguyen, Y. Lii, 1995 .

Integration of multi-level copper metallization into a high performance sub-0.25 /spl mu/m CMOS technology

T. Lii, M. Angyal, H. Kawasaki, 1998, Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th Anniversary of the MOSFET and 50th of the BJT. (Cat. No.98TH8350).

Integration of SiCN as a low /spl kappa/ etch stop and Cu passivation in a high performance Cu/low /spl kappa/ interconnect

Ertugrul Demircan, Larry Zhao, Steve Park, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).