B. Chan

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

Y. Yeo, Y. Huang, T. Lee, 2003, IEEE International Electron Devices Meeting 2003.

45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

Chenming Hu, Mong-Song Liang, Fu-Liang Yang, 2004, VLSIT 2004.

45nm Node Planar-SO1 Technology with 0.296pm2 6T-SUM Cell

Chenming Hu, Mong-Song Liang, Di-Hong Lee, 2004 .

5nm-gate nanowire FinFET

Chenming Hu, Yee-Chia Yeo, Mong-Song Liang, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..