K. Okabe

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

T. Sugii, T. Aoyama, H. Morioka, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

FEOL technologies for fabricating high performance logic and system LSI of 100 nm node

N. Tamura, M. Kase, K. Okabe, 2000, 2000 International Conference on Ion Implantation Technology Proceedings. Ion Implantation Technology - 2000 (Cat. No.00EX432).

A new salicide process (PASET) for sub-half micron CMOS

I. Sakai, K. Okabe, H. Abiko, 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

S. Satoh, T. Sugii, H. Ohta, 2007, 2007 IEEE International Electron Devices Meeting.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.