H. Minakata

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

T. Sugii, T. Aoyama, H. Morioka, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

M. Yamaguchi, Y. Tamura, H. Minakata, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Carrier profile designing to suppress systematic Vth variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects

S. Satoh, H. Minakata, Y. Momiyama, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs

M. Yamaguchi, T. Sakoda, H. Minakata, 2006, IEEE Transactions on Electron Devices.

Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

Y. Nara, H. Morioka, N. Tamura, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Novel shallow junction technology using decaborane (B/sub 10/H/sub 14/)

T. Sugii, I. Yamada, K. Goto, 1996, International Electron Devices Meeting. Technical Digest.

Segregation coefficient of impurities at polycrystalline Si/HfO2 interfaces

Kunihiro Suzuki, H. Minakata, M. Yamaguchi, 2005 .

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.