K. Sukegawa

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

T. Sugii, T. Aoyama, H. Morioka, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects

Tomohiro Kubo, Mitsuru Yamaji, S. Satoh, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

S. Satoh, T. Sugii, H. Ohta, 2007, 2007 IEEE International Electron Devices Meeting.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.