J. Park

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

M. Belyansky, X. Chen, R. Amos, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

H. J. Kim, J. J. Kim, S. W. Pae, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability

T. Jeong, S. Pae, H. C. Sagong, 2018, 2018 IEEE Symposium on VLSI Technology.