S. Balagopal

Reconfigurable Continuous-Time Delta-Sigma Analog-to-Digital Converters for Software-Defined and Multi-Standard Radios

V. Saxena, S. Balagopal, Hao-Wen Chen, 2011 .

Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time $$\Delta \Sigma$$ΔΣ modulator with 15 MHz bandwidth and 60 dB dynamic range

V. Saxena, S. Balagopal, Kehan Zhu, 2017 .

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-$$\Updelta\Upsigma$$ΔΣ ADC with 1.5 cycle quantizer delay and improved STF

Vishal Saxena, Kehan Zhu, Sakkarapani Balagopal, 2014 .

Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects

Vishal Saxena, Kehan Zhu, Wan Kuang, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning

Vishal Saxena, Kehan Zhu, Xinyu Wu, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time DR modulator with 15 MHz bandwidth and 60 dB dynamic range

V. Saxena, S. Balagopal, Kehan Zhu, 2016 .

High-Speed Delta-Sigma Data Converters for Next-Generation Wireless Communication

Sakkarapani Balagopal, S. Balagopal, 2014 .