Timothy O. Dickson

发表

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Alexander V. Rylyakov, Seongwon Kim, Herschel A. Ainspan, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Towards a sub-2.5V, 100-Gb/s Serial Transceiver

Sorin P. Voinigescu, Pascal Chevalier, Patrice Garcia, 2007, 2007 IEEE Custom Integrated Circuits Conference.

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

Daniel J. Friedman, John F. Bulzacchelli, Timothy O. Dickson, 2009, IEEE J. Solid State Circuits.

Wireless interconnects for clock distribution

Chih-Ming Hung, Kihong Kim, Brian A. Floyd, 2002, TAU '02.

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"

Mounir Meghelli, Herschel A. Ainspan, John F. Bulzacchelli, 2020, IEEE J. Solid State Circuits.

Silicon Integrated Circuits Incorporating Antennas

Z. Li, Yanping Ding, Chih-Ming Hung, 2006, IEEE Custom Integrated Circuits Conference 2006.

6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS

Mounir Meghelli, Herschel A. Ainspan, Timothy O. Dickson, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS

Timothy O. Dickson, Jonathan E. Proesel, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

Herschel A. Ainspan, Daniel J. Friedman, Sergey V. Rylov, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis

Sorin P. Voinigescu, Timothy O. Dickson, Paul Westergaard, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

A 1.8 pJ/bit $16 \times 16\;\text{Gb/s}$ Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

Mounir Meghelli, Herschel A. Ainspan, Daniel J. Friedman, 2016, IEEE Journal of Solid-State Circuits.

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

Yong Liu, Xiaoxiong Gu, Herschel A. Ainspan, 2012, IEEE Journal of Solid-State Circuits.

Introduction to the 31st Annual IEEE Compound Semiconductor Integrated Circuit Symposium

Timothy O. Dickson, Marko Sokolich, 2010 .

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Yong Liu, Mounir Meghelli, Herschel A. Ainspan, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

Byungsub Kim, Daniel J. Friedman, Yong Liu, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes

Sorin P. Voinigescu, Ekaterina Laskin, Edward S. Rogers, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

The feasibility of on-chip interconnection using antennas

Chih-Ming Hung, Jie Chen, Kihong Kim, 2005, ICCAD.

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS

Yong Liu, Daniel J. Friedman, Ankur Agrawal, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

Byungsub Kim, Daniel J. Friedman, Yong Liu, 2009, IEEE Journal of Solid-State Circuits.

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

Mounir Meghelli, Zeynep Toprak-Deniz, Seongwon Kim, 2018, IEEE Journal of Solid-State Circuits.

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Yong Liu, Daniel J. Friedman, Ankur Agrawal, 2012, IEEE Journal of Solid-State Circuits.

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

Mounir Meghelli, Zeynep Toprak-Deniz, Herschel A. Ainspan, 2020, IEEE Journal of Solid-State Circuits.

1 PRBS Generator in SiGe BiCMOS Technology

Sorin P. Voinigescu, E. Laskin, R. Beerkens, 2005 .

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman, 2015, IEEE Journal of Solid-State Circuits.