José A. Tierno

发表

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Alexander V. Rylyakov, Seongwon Kim, Herschel A. Ainspan, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

Aydin Babakhani, Jean-Olivier Plouchart, Alberto Valdes-Garcia, 2013, IEEE Journal of Solid-State Circuits.

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI

Alexander V. Rylyakov, Daniel J. Friedman, José A. Tierno, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Indirect phase noise sensing for self-healing voltage controlled oscillators

Lawrence T. Pileggi, Xin Li, Soner Yaldiz, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

Jean-Olivier Plouchart, Alberto Valdes-Garcia, Bodhisatwa Sadhu, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS

Aydin Babakhani, Jean-Olivier Plouchart, Alberto Valdes-Garcia, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Aydin Babakhani, Jean-Olivier Plouchart, Alberto Valdes-Garcia, 2013, IEEE Journal of Solid-State Circuits.

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

Alexander V. Rylyakov, Steven M. Nowick, Montek Singh, 2002, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI

Alexander V. Rylyakov, Daniel J. Friedman, José A. Tierno, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Adaptive energy-management features of the IBM POWER7 chip

Bishop Brock, Karthick Rajamani, Malcolm Allen-Ware, 2011, IBM J. Res. Dev..

Asynchronous circuits and systems in superconducting RSFQ digital technology

José A. Tierno, Theodore Van Duzer, Z. John Deng, 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

The energy and entropy of VLSI computations

Alain J. Martin, Rajit Manohar, José A. Tierno, 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

Aydin Babakhani, Jean-Olivier Plouchart, Alberto Valdes-Garcia, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Introducing the Adaptive Energy Management Features of the Power7 Chip

Bishop Brock, Karthick Rajamani, Charles Lefurgy, 2011, IEEE Micro.

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

Yong Liu, Bernard Brezzo, Daniel J. Friedman, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

Alexander V. Rylyakov, Steven M. Nowick, Montek Singh, 2010, IEEE Trans. Very Large Scale Integr. Syst..

Low-energy asynchronous memory design

Alain J. Martin, José A. Tierno, 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

Jean-Olivier Plouchart, Alexander V. Rylyakov, Herschel A. Ainspan, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

Aydin Babakhani, Jean-Olivier Plouchart, Alberto Valdes-Garcia, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS

Yong Liu, Daniel J. Friedman, Ankur Agrawal, 2012, 2012 IEEE International Solid-State Circuits Conference.

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits

Jean-Olivier Plouchart, Alberto Valdes-Garcia, Lawrence T. Pileggi, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS

Jean-Olivier Plouchart, Alexander V. Rylyakov, Herschel A. Ainspan, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 28 GHz Hybrid PLL in 32 nm SOI CMOS

Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman, 2014, IEEE Journal of Solid-State Circuits.

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

Bishop Brock, John B. Carter, Charles Lefurgy, 2013, IEEE Micro.

Active management of timing guardband to save energy in POWER7

Bishop Brock, John B. Carter, Charles Lefurgy, 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A 100-MIPS GaAs asynchronous microprocessor

Alain J. Martin, Drazen Borkovic, Tak-Kwan Lee, 1994, IEEE Design & Test of Computers.

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS

Jean-Olivier Plouchart, Scott K. Reynolds, Daniel J. Friedman, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

Bernard Brezzo, Sameh W. Asaad, Ralph Bellofatto, 2012, FPGA '12.

Asynchronous transpose-matrix architectures

Prabhakar Kudva, José A. Tierno, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

Asynchronous Parallel Prefix Computation

Rajit Manohar, José A. Tierno, R. Manohar, 1998, IEEE Trans. Computers.

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Yong Liu, Daniel J. Friedman, Ankur Agrawal, 2012, IEEE Journal of Solid-State Circuits.

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Yong Liu, Seongwon Kim, Daniel J. Friedman, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman, 2015, IEEE Journal of Solid-State Circuits.