K. Nakajima

41) On the serum ATP-ase (Proceedings of the 22nd Annual Meeting of the Japanese Circulation Society)

Magojiro Maekawa, Koichi Ogino, Shunji Motomura, 1958 .

Effect of soot introduced between sliding ceramic surfaces

K. Nakajima, K. Kitamura, Y. Imada, 1993 .

A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions

H. Koike, Y. Akasaka, K. Nakajima, 1996, International Electron Devices Meeting. Technical Digest.

Highly reliable CVD-WSi metal gate electrode for nMOSFETs

K. Nakajima, K. Sekine, K. Suguro, 2005, IEEE Transactions on Electron Devices.

Bare chip stacking structure for MCM production

K. Nakajima, C. R. Hodges, P. Kim, 1998, Proceedings. 1998 International Conference on Multichip Modules and High Density Packaging (Cat. No.98EX154).

High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime

Y. Akasaka, K. Nakajima, K. Suguro, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL

Y. Toyoshima, K. Nakajima, S. Kawanaka, 2008, 2008 Symposium on VLSI Technology.

Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

Y. Akasaka, Y. Toyoshima, K. Nakajima, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics

K. Nakajima, K. Suguro, K. Matsuo, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

Y. Akasaka, K. Nakajima, M. Kinugawa, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.