H. Park

发表

Novel heterodimensional diodes and transistors

M. Hurt, W.C.B. Peatman, Michael Shur, 1995 .

Two-dimensional metal-semiconductor field effect transistor for ultra low power circuit applications

W.C.B. Peatman, M. Shur, M. Shur, 1994, IEEE Electron Device Letters.

Michael S. Shur, W.C.B. Peatman, Boris Gelmont, 1993, Proceedings of IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits.

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

S. Narasimha, N. Zamdmer, J. Bruley, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

Woo-Hyeong Lee, S.K.H. Fung, P. Agnello, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Sub-60 nm physical gate length SOI CMOS

J. Sleight, E. Maciejewski, E. Nowak, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Sub-half-micrometer width 2-D MESFET

T. Ytterdal, M. Hurt, W.C.B. Peatman, 1996, IEEE Electron Device Letters.

Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors

Michael S. Shur, M. Asif Khan, M. Shur, 1996 .

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI

M. Sherony, S. Narasimha, Y. Kohyama, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

D. Mocuta, Y. Toyoshima, B.H. Lee, 2003, IEEE International Electron Devices Meeting 2003.

RF and DC characterization of P-channel Al/sub 0.5/Ga/sub 0.5/As/GaAs MODFETs with gate lengths as small as 0.25 mu m

Lester F. Eastman, Paul J. Tasker, William J. Schaff, 1989, Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,.