G. Beyer

Performance Comparison of Interconnect Technology and Architecture Options for Deep Submicron Technology Nodes

M. Van Hove, K. Maex, M. Stucchi, 2006, 2006 International Interconnect Technology Conference.

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

E. Beyne, K. Croes, A. Redolfi, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Chip package interaction (CPI): Thermo mechanical challenges in 3D technologies

E. Beyne, I. De Wolf, A. Ivankovic, 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

Reliability concerns in copper TSV's: Methods and results

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process

M. Van Hove, K. Maex, H. Meynen, 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).

Integration of the ZoneBOND™ temporary bonding material in backside processing for 3D applications

E. Beyne, A. Jourdain, A. La Manna, 2012, 2012 4th Electronic System-Integration Technology Conference.

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down

E. Beyne, A. Jourdain, S. Suhard, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Reliability of 3D package using wafer level underfill and low CTE epoxy mold compound materials

E. Beyne, C. Gerets, R. Daily, 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

HIGH DENSITY AND HIGH BANDWIDTH CHIP-TO-CHIP CONNECTIONS WITH 20μm PITCH FLIP-CHIP ON FAN-OUT WAFER LEVEL PACKAGE

E. Beyne, A. Phommahaxay, K. Rebibis, 2018, 2018 International Wafer Level Packaging Conference (IWLPC).

FET arrays as CPI sensors for 3D stacking and packaging characterization

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

The underfill-microbump interaction mechanism in 3D ICs: Impact and mitigation of induced stresses

E. Beyne, I. De Wolf, A. Ivankovic, 2014, 2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).

Characterization of Impact of Vertical Stress on FinFETs

E. Beyne, I. De Wolf, K. Vanstreels, 2019, 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC).

Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).