O. Richard

发表

Evidences of anodic-oxidation reset mechanism in TiN\NiO\Ni RRAM cells

R. Degraeve, L. Goux, B. Govoreanu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Thermally stable integrated Se-based OTS selectors with >20 MA/cm2 current drive, >3.103 half-bias nonlinearity, tunable threshold voltage and excellent endurance

L. Goux, B. Govoreanu, S. Kundu, 2017, 2017 Symposium on VLSI Technology.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology

L. Breuil, P. Blomme, J. Van Houdt, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

Metal Gate Technology using a Dy2O3 Dielectric Cap Approach for multiple-VT in NMOS FinFETs

S. Van Elshocht, B. Kaczer, P. Lehnen, 2007, 2007 IEEE International SOI Conference.

Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and excellent variability

B. Govoreanu, H. Bender, M. Jurczak, 2016, 2016 IEEE Symposium on VLSI Technology.

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

L. Witters, H. Bender, T. Chiarella, 2010, 2010 Symposium on VLSI Technology.

Ternary rare-earth metal oxide high-k layers on silicon oxide

Jürgen Schubert, Andre Stesmans, Hugo Bender, 2005 .

Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application

B. Govoreanu, A. Fantini, N. Jossart, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

T. Chiarella, C. Vrancken, A. Veloso, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

R. Rooyackers, B. Kaczer, S. Locorotondo, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Surface preparation and interfacial stability of high-k dielectrics deposited by atomic layer chemical vapor deposition

Wilfried Vandervorst, Marc Heyns, Matty Caymax, 2003 .

Plasma-enhanced chemical vapour deposition growth of Si nanowires with low melting point metal catalysts: an effective alternative to Au-mediated growth

Philippe M. Vereecken, Matty Caymax, Bart Blanpain, 2007 .

Conductive-AFM tomography for 3D filament observation in resistive switching devices

L. Goux, H. Bender, W. Vandervorst, 2013, 2013 IEEE International Electron Devices Meeting.

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

S. Locorotondo, H. Bender, T. Chiarella, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Scaling of high-k dielectrics towards sub-1nm EOT

S. De Gendt, D. Pique, S. Van Elshocht, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Processing Technologies for Advanced Ge Devices

Naoto Horiguchi, Jerome Mitard, Liesbeth Witters, 2017 .

Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology

C. Ortolland, A. Akheyar, T. Chiarella, 2006, 2009 Symposium on VLSI Technology.

Physical characterization of HfO 2 deposited on Ge substrates by MOCVD.

Stefan Kubicek, Marc Meuris, Matty Caymax, 2004 .

Barrier studies on porous silk semiconductor dielectric

Karen Maex, Bencherki Mebarki, Francesca Iacopi, 2003 .

Influence of the electron mean free path on the resistivity of thin metal films

Karen Maex, Bert Brijs, Ludo Froyen, 2004 .

Processing damage and electrical performance of porous dielectrics in narrow spaced interconnects

Karen Maex, Herbert Struyf, Michele Stucchi, 2004 .

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

E. Simoen, E. Vecchio, H. Bender, 2013, 2013 Symposium on VLSI Technology.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates

Marc Heyns, Marc Meuris, G. Raskin, 2005 .

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Deposition of HfO2 on germanium and the impact of surface pretreatments

Stefan Kubicek, T. Chiarella, Matty Caymax, 2004 .

3D-analysis of semiconductor structures by electron tomography

Hugo Bender, E. Sourty, O. Richard, 2007 .

Analysis of the size effect in electroplated fine copper wires and a realistic assessment to model copper resistivity

Karen Maex, Dagang Li, Sywert Brongersma, 2007 .

Controlled III/V Nanowire Growth by Selective-Area Vapor-Phase Epitaxy

Hugo Bender, Guy Brammertz, Matty Caymax, 2009 .