T. Furukawa

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

U. Gruening, D. Casarotto, J. Alsmeier, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)

Y. Taur, T. Furukawa, B. Davarik, 1989, International Technical Digest on Electron Devices Meeting.

High performance of planar double gate MOSFETs with thin backgate dielectrics

Leathen Shi, Meikei Ieong, E.C. Jones, 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

Effect of Al inclusion in HfO2 on the physical and electrical properties of the dielectrics

T. Ma, T. Tamagawa, T. Furukawa, 2002, IEEE Electron Device Letters.

A fundamental performance limit of optimized 3.3 V subquarter micron fully overlapped LDD MOSFETs

A. Bryant, E. Nowak, B. El-Kareh, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

Y. Taur, B. Davari, J. Warnock, 1988, Technical Digest., International Electron Devices Meeting.