Yasuhiko Hagihara

Chip-scale Si-photonics optical transceiver for a photonics-electronics convergence system

Ichiro Ogura, Junichi Fujikata, Kazuhiko Kurata, 2017, OPTO.

A 200MFLOPS 100MHz 64b BICMOS Vector-pipelined-processor

Tadayoshi Enomoto, Yasuhiko Hagihara, H. Yamada, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Floating-point datapaths with online built-in self speed test

Tatsuya Nakamura, H. Yamada, Yasuhiko Hagihara, 1997 .

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI

Tadayoshi Enomoto, Yasuhiko Hagihara, H. Yamada, 1991 .

Domino Logic Synthesis System and its Applications

Takeshi Yoshimura, Yuichi Nakamura, Yasuhiko Hagihara, 2006, J. Circuits Syst. Comput..

A hardware overview of SX-6 and SX-7 supercomputer

Yasuhiko Hagihara, Kenji Kitagawa, Yasushi Kanoh, 2003 .

Design for testability in a 200 MFLOPS vector-pipelined processor (VPP)-ULSI

M. Takada, Yasuhiko Hagihara, H. Yamada, 1992, Proceedings First Asian Test Symposium (ATS `92).

Timing optimization methodology based on replacing flip-flops by latches

Takeshi Yoshimura, Yuichi Nakamura, Yasuhiko Hagihara, 2004 .

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications

Masahiro Nomura, Yasuhiko Hagihara, Yoshiharu Aimoto, 2006, IEEE Journal of Solid-State Circuits.