Masataka Hoshino

Current Status of Research and Development for Three-Dimensional Chip Stack Technology

Manabu Bonkohara, Yoshihiro Tomita, Y. Yamaji, 2001 .

Development of less expensive process technologies for three-dimensional chip stacking with through-vias

Kazumasa Tanida, Mitsuo Umemoto, Toshihiro Yonezawa, 2004 .

Semi‐insulator‐embedded InGaAsP/InP flat‐surface buried heterostructure laser

Hiroshi Ishikawa, Shigenobu Yamakoshi, Junji Komeno, 1985 .

Copper Via Filling Electrodeposition of High Aspect Ratio Through Chip Electrodes Used for the Three Dimensional Packaging

Seung Jin Oh, M. Tomisaka, Hitoshi Yonemura, 2003 .

Development of advanced 3D chip stacking technology with ultra-fine interconnection

M. Tomisaka, Hitoshi Yonemura, Hiroshi Terao, 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI

M. Tomisaka, Hitoshi Yonemura, Kenji Takahashi, 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

Electroplating Cu fillings for through-vias for three-dimensional chip stacking

M. Tomisaka, Hitoshi Yonemura, Jian Jun Sun, 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).