N. Yoshida

Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

B. Parvais, A. Brand, N. Horiguchi, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology

B. Parvais, E. Simoen, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

B. Parvais, S. Van Elshocht, A. Brand, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

A. Brand, R. Hung, S. Gandikota, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.