Kewal K. Saluja

发表

A yield improvement methodology using pre- and post-silicon statistical clock scheduling

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

A Methodology for Identifying High Timing Variability Paths in Complex Designs

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Enhancement of Clock Delay Faults Testing

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2011, 2011 Sixteenth IEEE European Test Symposium.

Deployment of fault tolerant sensor networks for target detection

Kewal K. Saluja, Thomas Clouqueur, 2003 .

A Novel Approach for Testing Memories Using a Built-In Self Testing Technique

Kewal K. Saluja, Kim T. Le, K. T. Le, 1986, International Test Conference.

Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies

Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao, 2009, 2009 Asian Test Symposium.

State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size

Dong Hyun Baik, Kewal K. Saluja, 2005, 14th Asian Test Symposium (ATS'05).

Value-Fusion versus Decision-Fusion for Fault-tolerance in Collaborative Target Detection in Sensor Networks

Kuang-Ching Wang, Parameswaran Ramanathan, Kewal K. Saluja, 2001 .

Design and analysis of multiple weight linear compactors of responses containing unknown values

Hideo Fujiwara, Kewal K. Saluja, Thomas Clouqueur, 2005, IEEE International Conference on Test, 2005..

Design for diagnosability of CMOS circuits

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints

Kewal K. Saluja, Spencer K. Millican, 2015, 2015 28th International Conference on VLSI Design.

Diagnosis for Bridging Faults on Clock Lines

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

SCINDY: logic crosstalk delay fault simulation in sequential circuits

Kewal K. Saluja, Marong Phadoongsidhi, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Xiaoqing Wen, Kazumi Hatayama, Kohei Miyase, 2008, 2008 13th European Test Symposium.

Calibrating Nonlinear Mobile Sensors

Parameswaran Ramanathan, Chao Wang, Kewal K. Saluja, 2008, 2008 5th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks.

Electrical model for program disturb faults in non-volatile memories

Kewal K. Saluja, Mohammad Gh. Mohammad, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Estimation of maximum power-up current

Fei Li, Kewal K. Saluja, Lei He, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Efficient Test Set Modification for Capture Power Reduction

Xiaoqing Wen, Kohei Miyase, Kewal K. Saluja, 2005, J. Low Power Electron..

An implementation and analysis of a concurrent built-in self-test technique

Kewal K. Saluja, Rajiv Sharma, 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

Scheduling tests for VLSI systems under power constraints

Vishwani D. Agrawal, Kewal K. Saluja, Richard M. Chou, 1997, IEEE Trans. Very Large Scale Integr. Syst..

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2017, J. Electron. Test..

On low-capture-power test generation for scan testing

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Fault tolerance in collaborative sensor networks for target detection

Parameswaran Ramanathan, Kewal K. Saluja, Thomas Clouqueur, 2004, IEEE Transactions on Computers.

Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions

Parameswaran Ramanathan, Chao Wang, Kewal K. Saluja, 2009, 2009 6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks.

Combinational automatic test pattern generation for acyclic sequential circuits

Vishwani D. Agrawal, Kewal K. Saluja, Yong Chang Kim, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fault Tolerance through Invariant Checking for the Lanczos Eigensolver

Parameswaran Ramanathan, Kewal K. Saluja, Felix Loh, 2020, 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID).

Theory, Analysis and Implementation of an On-LineBIST Technique

Kewal K. Saluja, Rajiv Sharma, 1993 .

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation

Xiaoqing Wen, Kohei Miyase, Kewal K. Saluja, 2006, 2006 International Conference on Computer Design.

CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities

Parameswaran Ramanathan, Kewal K. Saluja, Spencer K. Millican, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

An optimized testable architecture for finite state machines

Kewal K. Saluja, Ting-Yu Kuo, Chun-Yeh Liu, 1995, Proceedings 13th IEEE VLSI Test Symposium.

False Path Aware Timing Yield Estimation under Variability

Lin Xie, Azadeh Davoodi, Kewal K. Saluja, 2009, 2009 27th IEEE VLSI Test Symposium.

Built-In Self-Testing RAM:

Kewal K. Saluja, Siew H. Sng, 1987 .

Organization and analysis of a gracefully-degrading interleaved memory system

Dhiraj K. Pradhan, Kewal K. Saluja, Gurindar S. Sohi, 1987, ISCA '87.

A built-in self-test algorithm for row/column pattern sensitive faults in RAMs

Kewal K. Saluja, M. Franklin, K. Kinoshita, 1990 .

Fault models and test generation for IDDQ testing: embedded tutorial

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, ASP-DAC.

DRMA: dynamically reconfigurable MPSoC architecture

Sri Parameswaran, Kewal K. Saluja, Roshan G. Ragel, 2013, GLSVLSI '13.

Low-Area Wrapper Cell Design for Hierarchical SoC Testing

Kewal K. Saluja, Kyuchull Kim, 2009, J. Electron. Test..

Soft error reduction through gate input dependent weighted sizing in combinational circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2011, 2011 12th International Symposium on Quality Electronic Design.

On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On fault deletion problem in concurrent fault simulation for synchronous sequential circuits

Kewal K. Saluja, Kyuchull Kim, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

On Minimization of Test Application Time for RAS

Hideo Fujiwara, Adit D. Singh, Kewal K. Saluja, 2010, 2010 23rd International Conference on VLSI Design.

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead

Kozo Kinoshita, Hideo Fujiwara, Kewal K. Saluja, 1985, ITC.

Trends in Fault Tolerant Computing

Kewal K. Saluja, Cs Venkatraman, 1980 .

Synthesizing finite state machines for minimum length synchronizing sequence using partial scan

Kewal K. Saluja, Ning Jiang, Richard M. Chou, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

Reduction of Fault Dictionary Size by Optimizing the Order of Test Patterns Application

Kewal K. Saluja, Yoshinobu Higami, Hiroshi Takahashi, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Sequential test generation with reduced test clocks for partial scan designs

Kewal K. Saluja, Soo Young Lee, 1994, Proceedings of IEEE VLSI Test Symposium.

A Study of Capture-Safe Test Generation Flow for At-Speed Testing

Xiaoqing Wen, Kazumi Hatayama, Kohei Miyase, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch

Hideo Fujiwara, Kewal K. Saluja, Yoshiyuki Nakamura, 2006, IEICE Trans. Inf. Syst..

Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST

Hideo Tamamoto, Kewal K. Saluja, Hiroshi Yokoyama, 2010, 2010 19th IEEE Asian Test Symposium.

Reduction of target fault list for crosstalk-induced delay faults by using layout constraints

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

BIST-PLA: A Built-In Self-Test Design of Large Programmable Logic Arrays

Kewal K. Saluja, Shambhu J. Upadhyaya, Chun-Yeh Liu, 1987, 24th ACM/IEEE Design Automation Conference.

Parallel computation of LFSR signatures

Kewal K. Saluja, B. Narendran, M. Franklin, 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).

Stress test for disturb faults in non-volatile memories

Kewal K. Saluja, Mohammad Gh. Mohammad, 2003, 2003 Test Symposium.

Testing micropipelined asynchronous circuits

Kewal K. Saluja, M. L. King, 2004 .

Combinational test generation for various classes of acyclic sequential circuits

Vishwani D. Agrawal, Kewal K. Saluja, Yong Chang Kim, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Flash memory disturbances: modeling and test

Kewal K. Saluja, Mohammad Gh. Mohammad, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

On test pattern compaction using random pattern fault simulation

Kewal K. Saluja, Seiji Kajihara, 1998, Proceedings Eleventh International Conference on VLSI Design.

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2017, IEICE Trans. Inf. Syst..

Testable Design of Single-Output Sequential Machines Using Checking Experiments

Kewal K. Saluja, Ramaswami Dandapani, K. Saluja, 1986, IEEE Transactions on Computers.

Incorporating performance and testability constraints during binding in high-level synthesis

Kewal K. Saluja, Rajiv Jain, Ashutosh Mujumdar, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Yield-driven, false-path-aware clock skew scheduling

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, 2005, IEEE Design & Test of Computers.

Efficient test vectors for ISCAS sequential benchmark circuits

Kewal K. Saluja, Soo Young Lee, Soo Young Lee, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Instruction-based delay fault self-testing of pipelined processor cores

Hideo Fujiwara, Kewal K. Saluja, Virendra Singh, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A correlation matrix method of clock partitioning for sequential circuit testability

Vishwani D. Agrawal, Kewal K. Saluja, Yong Chang Kim, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Outstanding challenges in testing nanotechnology based integrated circuits

Kewal K. Saluja, 2003, 2003 Test Symposium.

Behavioral synthesis of testable designs

Kewal K. Saluja, Rajiv Jain, Ashutosh Mujumdar, 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

Analytic modeling of detection latency in mobile sensor networks

Parameswaran Ramanathan, Kewal K. Saluja, Tai-Lin Chin, 2006, IPSN.

Diagnosis of Delay Faults in the Presence of Clock Delays Considering Hazards

Kewal K. Saluja, Hiroshi Takahashi, Yoshinobu Higami, 2015 .

Static test compaction for IDDQ testing of sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1998, Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232).

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability

Hideo Fujiwara, Kewal K. Saluja, Satoshi Ohtake, 2007, IEICE Trans. Inf. Syst..

A yield improvement methodology using pre- and post-silicon statistical clock scheduling

Jeng-Liang Tsai, Charlie Chung-Ping Chen, Kewal K. Saluja, 2004, ICCAD 2004.

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 2005, IEICE Trans. Inf. Syst..

Fault diagnosis for physical defects of unknown behaviors

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 2003, 2003 Test Symposium.

Reduction of dynamic memory usage in concurrent fault simulation for synchronous sequential circuits

Kewal K. Saluja, K. Kim, 1992, Proceedings First Asian Test Symposium (ATS `92).

Testing Computer Hardware through Data Compression in Space and Time

Mark G. Karpovsky, Kewal K. Saluja, M. Karpovsky, 1983, ITC.

Exclusive test and its applications to fault diagnosis

Vishwani D. Agrawal, Dong Hyun Baik, Kewal K. Saluja, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Guest Editorial

Kwang-Ting Cheng, Kewal K. Saluja, Hans-Joachim Wunderlich, 1997, Journal of electronic testing.

A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits

Kewal K. Saluja, Spencer K. Millican, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Event-centric simulation of crosstalk pulse faults in sequential circuits

Kewal K. Saluja, Marong Phadoongsidhi, 2003, Proceedings 21st International Conference on Computer Design.

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors

Kewal K. Saluja, Pramod Subramanyan, Virendra Singh, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Test Scheduling and Control for VLSI Built-In Self-Test

Kewal K. Saluja, Charles R. Kime, Gary L. Craig, 1988, IEEE Trans. Computers.

Testable design of large random access memories

Kewal K. Saluja, Kim T. Le, 1984, Integr..

Privacy Assurances in Multiple Data-Aggregation Transactions

Parameswaran Ramanathan, Kewal K. Saluja, Kim T. Le, 2013, ICISC.

Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model

Parameswaran Ramanathan, Kewal K. Saluja, Rehan Ahmed, 2016, TECS.

Exposure of variable speed targets through a sensor field

Kewal K. Saluja, Thomas Clouqueur, Parmesh Ramanathan, 2003, Sixth International Conference of Information Fusion, 2003. Proceedings of the.

An alternative method of generating tests for path delay faults using N/sub i/-detection test sets

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2002, 2002 Pacific Rim International Symposium on Dependable Computing, 2002. Proceedings..

Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2012, 2012 25th International Conference on VLSI Design.

Digital Testing -- Basics to Advanced Research Issues

Kewal K. Saluja, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

WSN19-3: Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles

Parameswaran Ramanathan, Kewal K. Saluja, Tai-Lin Chin, 2006, IEEE Globecom 2006.

Design of a BIST RAM with row/column pattern sensitive fault detection capability

Kozo Kinoshita, Kewal K. Saluja, Manoj Franklin, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

A New Method for Low-Capture-Power Test Generation for Scan Testing

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2006, IEICE Trans. Inf. Syst..

Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations

Parameswaran Ramanathan, Kewal K. Saluja, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Temperature Dependent Test Scheduling for Multi-core System-on-Chip

Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao, 2011, 2011 Asian Test Symposium.

Fault Diagnosis of Physical Defects Using Unknown Behavior Model

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 2005, Journal of Computer Science and Technology.

Efficient signature-based fault diagnosis using variable size windows

Hiroshi Takahashi, Kewal K. Saluja, Thomas Clouqueur, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000 .

Exploiting path delay test generation to develop better TDF tests for small delay defects

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2017, 2017 IEEE International Test Conference (ITC).

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors

Hideo Fujiwara, Kewal K. Saluja, Virendra Singh, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An efficient algorithm for bipartite PLA folding

Kewal K. Saluja, Chun-Yeh Liu, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An algorithm to reduce test application time in full scan designs

Kewal K. Saluja, Soo Young Lee, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Gate input reconfiguration for combating soft errors in combinational circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2010, 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W).

Privacy Assurance in Data-Aggregation for Multiple MAX Transactions

Parameswaran Ramanathan, Kewal K. Saluja, Kim T. Le, 2015, 2015 IEEE 39th Annual Computer Software and Applications Conference.

A concurrent fault simulation for crosstalk faults in sequential circuits

Kewal K. Saluja, Kim T. Le, Marong Phadoongsidhi, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

On Minimally Testable Logic Networks

Sudhakar M. Reddy, Kewal K. Saluja, 1974, IEEE Transactions on Computers.

Diagnosis of Delay Faults Considering Hazards

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

On NBTI Degradation Process in Digital Logic Circuits

Kewal K. Saluja, Xiangning Yang, Eric F. Weglarz, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

An algorithm to test reconfigured RAMs

Kewal K. Saluja, Manoj Franklin, 1994, Proceedings of 7th International Conference on VLSI Design.

Sensor Deployment Strategy for Detection of Targets Traversing a Region

Parameswaran Ramanathan, Kewal K. Saluja, Thomas Clouqueur, 2003, Mob. Networks Appl..

Synchronous Sequential Machines: A Modular and Testable Design

Kewal K. Saluja, 1980, IEEE Transactions on Computers.

Microprocessor Based Remote Metering System

Kewal K. Saluja, I Lawrence, B Hunter, 1983 .

Fault tolerance through re-execution in multiscalar architecture

Kewal K. Saluja, Faisal Rashid, Paramesw aran Ramanathan, 2000, Proceeding International Conference on Dependable Systems and Networks. DSN 2000.

Modeling latency—lifetime trade-off for target detection in mobile sensor networks

Parameswaran Ramanathan, Chao Wang, Kewal K. Saluja, 2010, TOSN.

DX-compactor: distributed X-compaction for SoCs

Kewal K. Saluja, Virendra Singh, Reshma C. Jumani, 2009, GLSVLSI '09.

A study of time-redundant fault tolerance techniques for high-performance pipelined computers

Kewal K. Saluja, Gurindar S. Sohi, Manoj Franklin, 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

Correction to A Data Compression Technique for Built-In Self-Test

Sudhakar M. Reddy, Mark G. Karpovsky, Kewal K. Saluja, 1989 .

Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits

Kewal K. Saluja, Spencer K. Millican, 2012, 2012 IEEE 21st Asian Test Symposium.

A Class of Linear Space Compactors for Enhanced Diagnostic

Kewal K. Saluja, Thomas Clouqueur, Hideo Fujiwara, 2005, 14th Asian Test Symposium (ATS'05).

Software-based delay fault testing of processor cores

Hideo Fujiwara, Kewal K. Saluja, Virendra Singh, 2003, 2003 Test Symposium.

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testing of hard faults in simultaneous multi-threaded processors

Kewal K. Saluja, T. M. Mak, Eric F. Weglarz, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

A low cost approach to calibrate on-chip thermal sensors

Parameswaran Ramanathan, Nam Sung Kim, Kewal K. Saluja, 2011, 2011 12th International Symposium on Quality Electronic Design.

A new ATPG method for efficient capture power reduction during scan testing

Kozo Kinoshita, Kohei Miyase, Kewal K. Saluja, 2006, 24th IEEE VLSI Test Symposium.

Design and Analysis of a Gracefully Degrading Interleaved Memory System

Dhiraj K. Pradhan, Kewal K. Saluja, Gurindar S. Sohi, 1990, IEEE Trans. Computers.

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2013, IEICE Trans. Inf. Syst..

Exposure for collaborative detection using mobile sensor networks

Kuang-Ching Wang, Parameswaran Ramanathan, Kewal K. Saluja, 2005, IEEE International Conference on Mobile Adhoc and Sensor Systems Conference, 2005..

An accurate flip-flop selection technique for reducing logic SER

Mikko H. Lipasti, Kewal K. Saluja, Eric L. Hill, 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

An Efficient Algorithm for Sequential Circuit Test Generation

Kewal K. Saluja, Soo Young Lee, Todd P. Kelsey, 1993, IEEE Trans. Computers.

Embedded RAM testing

Kewal K. Saluja, M. Franklin, 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

Sequential circuit testing: from DFT to SFT

Kewal K. Saluja, Richard M. Chou, K. Saluja, 1997, Proceedings Tenth International Conference on VLSI Design.

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Combating NBTI Degradation via Gate Sizing

Kewal K. Saluja, Xiangning Yang, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Observation time reduction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

SEU tolerant SRAM cell

Masahiro Fujita, Kewal K. Saluja, Virendra Singh, 2011, 2011 12th International Symposium on Quality Electronic Design.

ORGANIZATION AND ANALYSIS OF A GRACEFULLY-DEGRADING

Kewal K. Saluja, Dhiraj Pradhan, Gurindar Sohi, 1987 .

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Energy-efficient redundant execution for chip multiprocessors

Kewal K. Saluja, Pramod Subramanyan, Virendra Singh, 2010, GLSVLSI '10.

A Per-Test Fault Diagnosis Method Based on the X-Fault Model

Kozo Kinoshita, Xiaoqing Wen, Kohei Miyase, 2006, IEICE Trans. Inf. Syst..

AN ALGORITHM TO TEST RAMS FOR PHYSICAL NEIGHBORHOOD PATTERN SENSITIVE FAULTS

Kewal K. Saluja, Manoj Franklin, 1991, 1991, Proceedings. International Test Conference.

Instruction-based delay fault self-testing of processor cores

Hideo Fujiwara, Kewal K. Saluja, Virendra Singh, 2004, 17th International Conference on VLSI Design. Proceedings..

Combinational test generation for acyclic sequential circuits using a balanced ATPG model

Vishwani D. Agrawal, Kewal K. Saluja, Yong Chang Kim, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Fault Tolerance through Invariant Checking for Iterative Solvers

Parameswaran Ramanathan, Kewal K. Saluja, Felix Loh, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

SEU tolerant SRAM for FPGA applications

Masahiro Fujita, Kewal K. Saluja, Virendra Singh, 2010, 2010 International Conference on Field-Programmable Technology.

Message from the Technical Program Co-Chairs

Kewal K. Saluja, Gaurab Banerjee, 2003, WORDS.

Thermal-Aware Test Scheduling Using On-chip Temperature Sensors

Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao, 2011, 2011 24th Internatioal Conference on VLSI Design.

False path and clock scheduling based yield-aware gate sizing

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

On Detecting Transition Faults in the Presence of Clock Delay Faults

Kewal K. Saluja, Yoshinobu Higami, Shin-ya Kobayashi, 2011, 2011 Asian Test Symposium.

Progressive random access scan: a simultaneous solution to test power, test data volume and test time

Dong Hyun Baik, Kewal K. Saluja, K. Saluja, 2005, IEEE International Conference on Test, 2005..

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

Kewal K. Saluja, Pramod Subramanyan, Virendra Singh, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Minimization of Reed–Muller Canonic Expansion

Kewal K. Saluja, E. H. Ong, K. Saluja, 1979, IEEE Transactions on Computers.

An efficient signature computation method

Kewal K. Saluja, Chin-Foo See, 1992, IEEE Design & Test of Computers.

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, Systems and Computers in Japan.

Sensor deployment strategy for target detection

Parameswaran Ramanathan, Kewal K. Saluja, Thomas Clouqueur, 2002, WSNA '02.

Fault Detecting Test Sets for Reed-Muller Canonic Networks

Sudhakar M. Reddy, Kewal K. Saluja, 1975, IEEE Transactions on Computers.

Methods for dynamic test vector compaction in sequential test generation

Kewal K. Saluja, Timothy John Lambert, 1996, Proceedings of 9th International Conference on VLSI Design.

Test application time minimization for RAS using basis optimization of column decoder

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A New Approach to the Design of Built-In Self-

Kewal K. Saluja, Shambhu Upadhyaya, S. Mourad, 1988 .

Hypergraph Coloring and Reconfigured RAM Testing

Kewal K. Saluja, Manoj Franklin, 1994, IEEE Trans. Computers.

Testing Technique for Digital Circuits

Kewal K. Saluja, Rajiv Sharma, C. R. Kime, 1988 .

Zero cost testing of check bits in RAMs with on-chip ECC

Parameswaran Ramanathan, Kewal K. Saluja, Michael J. Franklin, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Random access scan: a solution to test power, test data volume and test time

Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara, 2004, 17th International Conference on VLSI Design. Proceedings..

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation

Masaki Hashizume, Hiroshi Takahashi, Kewal K. Saluja, 2013, 2013 22nd Asian Test Symposium.

Temperature Minimization Using Power Redistribution in Embedded Systems

Parameswaran Ramanathan, Kewal K. Saluja, Rehan Ahmed, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

Kewal K. Saluja, Kyuchull Kim, 1996 .

Testable synthesis and testing of finite state machines

Kewal K. Saluja, Chen-Yeh Liu, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Identifying high variability speed-limiting paths under aging

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2017, 2017 18th IEEE Latin American Test Symposium (LATS).

Power and thermal constrained test scheduling

Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao, 2009, 2009 International Test Conference.

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding

Kewal K. Saluja, Pramod Subramanyan, Virendra Singh, 2010, 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN).

AN Alternative Test Generation for Path Delay Faults by Using Ni-Detection Test Sets

Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu, 2003 .

Built-in self-testing of random-access memories

Kewal K. Saluja, Manoj Franklin, 1990, Computer.

An algorithm to reduce test application time in full scan designs

Kewal K. Saluja, Soo Young Lee, 1992, ICCAD.

Efficient techniques for reducing IDDQ observation time for sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

A new approach to the design of built-in self-testing PLAs for high fault coverage

Kewal K. Saluja, Shambhu J. Upadhyaya, S. Upadhyaya, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Lin Xie, Azadeh Davoodi, Kewal K. Saluja, 2010, Design Automation Conference.

A Diagnosable Design of Programmable Logic Arrays

Kewal K. Saluja, 1982 .

Static timing analysis of irreversible crosstalk noise pulse faults

Kewal K. Saluja, Marong Phadoongsidhi, 2004, 17th International Conference on VLSI Design. Proceedings..

A Tutorial on Built-In Self-Test, Part 2: Applications

Vishwani D. Agrawal, Kewal K. Saluja, Charles R. Kime, 1993, IEEE Des. Test Comput..

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2006, Asia and South Pacific Conference on Design Automation, 2006..

On thermal utilization of periodic task sets in uni-processor systems

Parameswaran Ramanathan, Kewal K. Saluja, Rehan Ahmed, 2013, 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications.

Test application time reduction for sequential circuits with scan

Kewal K. Saluja, Soo Young Lee, Soo Young Lee, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimizing program disturb fault tests using defect-based testing

Kewal K. Saluja, Mohammad Gh. Mohammad, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On per-test fault diagnosis using the X-fault model

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2004, ICCAD 2004.

Multiple faults: modeling, simulation and test

Vishwani D. Agrawal, Kewal K. Saluja, Yong Chang Kim, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan

Dong Hyun Baik, Kewal K. Saluja, Kim T. Le, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Energy Estimation of the Memory Subsystem in Multiprocessor Systems

Mikko H. Lipasti, Kewal K. Saluja, Eric F. Weglarz, 2006, J. Low Power Electron..

SIGNATURE TECHNIQUES IN FAULT DETECTION AND LOCATION

Kewal K. Saluja, Shambhu Upadhyaya, S. Upadhyaya, 1985 .

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

Hideo Fujiwara, Kewal K. Saluja, Yoshiyuki Nakamura, 2006, 2006 15th Asian Test Symposium.

A Novel Approach to Random Pattern Testing of Sequential Circuits

Kewal K. Saluja, Lama Nachman, Shambhu J. Upadhyaya, 1998, IEEE Trans. Computers.

A Heuristic Measure to Maximize Detected Faults per Test

Kewal K. Saluja, Kim T. Le, K. T. Le, 1998, J. Electron. Test..

Testing check bits at no cost in RAMs with on-chip ECC

Kewal K. Saluja, Parmesh Ramanathan, M. Franklin, 1993 .

Fault Tolerant Cholesky Factorization on GPUs

Parameswaran Ramanathan, Kewal K. Saluja, Felix Loh, 2018, 2018 IEEE/ACM 8th Workshop on Fault Tolerance for HPC at eXtreme Scale (FTXS).

Fault diagnosis for static CMOS circuits

Kozo Kinoshita, Hideo Tamamoto, Kewal K. Saluja, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Detection of inter-port bridging faults in dual-port memories

Kewal K. Saluja, Ho-Yong Choi, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Yield-Driven, Clock Skew Scheduling

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, 2005 .

Modified T-Flip-Flop based scan cell for RAS

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2010, 2010 15th IEEE European Test Symposium.

Fast computation of MISR signatures

Kewal K. Saluja, Manoj Franklin, Kyuchull Kim, 1995, Proceedings of the 8th International Conference on VLSI Design.

Fast test generation for sequential circuits

Kewal K. Saluja, Todd P. Kelsey, K. Saluja, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

NBTI Degradation: A Problem or a Scare?

Kewal K. Saluja, Warin Sootkaneung, Shriram Vijayakumar, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Testing superscalar processors in functional mode

Hideo Fujiwara, Kewal K. Saluja, Virendra Singh, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2008, IEICE Trans. Inf. Syst..

An Enhancement of LSSD to Reduce Test Pattern Generation Effort and Increase Fault Coverage

Kewal K. Saluja, 1982, DAC 1982.

On per-test fault diagnosis using the X-fault model

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Low-capture-power test generation for scan-based at-speed testing

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2005, IEEE International Conference on Test, 2005..

Detection of bridging faults in programmable logic arrays

Sudhakar M. Reddy, Kewal K. Saluja, C.-Y. Liu, 1992 .

Transistor Leakage Fault Diagnosis for CMOS Circuits

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1998 .

A watchdog processor based general rollback technique with multiple retries

Kewal K. Saluja, Shambhu J. Upadhyaya, 1986, IEEE Transactions on Software Engineering.

Improved test generation for high-activity circuits

Kewal K. Saluja, Kyuchull Kim, 1990, IEEE Design & Test of Computers.

Fault simulation techniques to reduce IDDQ measurement vectors for sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Sequential test generators: past, present and future

Kewal K. Saluja, Yong Chang Kim, 1998, Integr..

Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays

Kewal K. Saluja, Yoshinobu Higami, Shin-ya Kobayashi, 2016, IPSJ Trans. Syst. LSI Des. Methodol..

Testing Core-Based System-on-a-Chip Designs

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2001 .

Easily Diagnosable Design at System Level

Kewal K. Saluja, Bdo Anderson, 1981 .

A method of reducing aliasing in a built-in self-test environment

Kewal K. Saluja, Keiho Akiyama, K. Saluja, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An Enhancement of LSSD to Reduce Test Pattern Generation Effort and Increase Fault Coverage

Kewal K. Saluja, K. Saluja, 1982, 19th Design Automation Conference.

Implementing high availability memory with a duplication cache

James E. Smith, Norman P. Jouppi, Kewal K. Saluja, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

Collaborative patrolling for target detection using mobile sensor networks

Parameswaran Ramanathan, Kewal K. Saluja, Tai-Lin Chin, 2010, 2010 International Conference on Wireless Communications & Signal Processing (WCSP).

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

Kozo Kinoshita, Xiaoqing Wen, Kohei Miyase, 2008, J. Electron. Test..

On techniques for handling soft errors in digital circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2010, 2010 IEEE International Test Conference.

Transistor Leakage Fault Diagnosis with I DDQ and Logic Information

Kozo Kinoshita, Hideo Tamamoto, Kewal K. Saluja, 1998 .

A Self Testing Microprocessor Based System

Kewal K. Saluja, Sj Wiche, 1980 .

An experimental study to determine task size for rollback recovery systems

Kewal K. Saluja, Shambhu Upadhyaya, 1988 .

A Data Compression Technique for Built-In Self-Test

Sudhakar M. Reddy, Mark G. Karpovsky, Kewal K. Saluja, 1988, IEEE Trans. Computers.

Design of Programmable Logic Arrays for Parallel Testing

Kozo Kinoshita, Kewal K. Saluja, C. Boswell, 1985, Comput. Syst. Sci. Eng..

Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach

Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao, 2011, J. Electron. Test..

TEST SCHEDULING IN TESTABLE VLSI CIRCUITS

Kewal K. Saluja, C. R. Kime, K. Saluja, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

A Simplified Algorithm for Testing Microprocessors

Li Shen, Kewal K. Saluja, Stephen Y. H. Su, 1983, ITC.

Testable sequential circuit design: a partition and resynthesis approach

Kewal K. Saluja, Richard M. Chou, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Testing micropipelined asynchronous circuits

Kewal K. Saluja, Matthew L. King, 2004, 2004 International Conferce on Test.

Design for strong testability of RTL data paths to provide complete fault efficiency

Toshimitsu Masuzawa, Hideo Fujiwara, Kewal K. Saluja, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations

Kewal K. Saluja, Tsuyoshi Iwagaki, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling

Kewal K. Saluja, Spencer K. Millican, 2013, 2013 22nd Asian Test Symposium.

Reliability enhancement by submodule redundancy

Kewal K. Saluja, Shambhu Upadhyaya, H. Pham, 1990, Annual Proceedings on Reliability and Maintainability Symposium.

CCSTG: an efficient test pattern generator for sequential circuits

Kewal K. Saluja, Kyuchull Kim, K. Saluja, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing

Xiaoqing Wen, Kohei Miyase, Kewal K. Saluja, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, J. Electron. Test..

Row/column pattern sensitive fault detection in RAMs via built-in self-test

Kozo Kinoshita, Kewal K. Saluja, Manoj Franklin, 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

組合せ回路および順序回路に対する診断用テスト圧縮法(LSIシステムの実装・モジュール化・インタフェース技術, テスト技術)

Kewal K. Saluja, 高橋寛, 樋上喜信, 2005 .

A Novel ATPG Method for Capture Power Reduction during Scan Testing

Kozo Kinoshita, Xiaoqing Wen, Kohei Miyase, 2007, IEICE Trans. Inf. Syst..

HYSIM: Hybrid Fault Simulation for Synchronous

Kewal K. Saluja, Kyuchull Kim, 1996 .

Simulating program disturb faults in flash memories using SPICE compatible electrical model

Kewal K. Saluja, Mohammad Gh. Mohammad, 2003 .

Easily Testable Two-Dimensional Cellular Logic Arrays

Sudhakar M. Reddy, Kewal K. Saluja, 1974, IEEE Transactions on Computers.

A Tutorial on Built-in Self-Test. I. Principles

Vishwani D. Agrawal, Kewal K. Saluja, Charles R. Kime, 1993, IEEE Des. Test Comput..

Minimizing energy consumption for high-performance processing

Mikko H. Lipasti, Kewal K. Saluja, Eric F. Weglarz, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Simulation-based diagnosis for crosstalk faults in sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2001, Proceedings 10th Asian Test Symposium.

Delay Fault Testing of Processor Cores in Functional Mode

Hideo Fujiwara, Kewal K. Saluja, Virendra Singh, 2005, IEICE Trans. Inf. Syst..

New Algorithms for Testing Instruction Decoding Function of Microprocessors

Kewal K. Saluja, Li Shen, Stephen Y. H. Su, 1983 .

Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors

Yen-Ting Lin, Kewal K. Saluja, Seapahn Megerian, 2011, Ad Hoc Networks.

WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements

Kewal K. Saluja, Abhishek A. Sinkar, Chunhua Yao, 2009, 2009 22nd International Conference on VLSI Design.

Detecting unauthorized activities using a sensor network

Parameswaran Ramanathan, Kewal K. Saluja, Thomas Clouqueur, 2004 .

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults

Kozo Kinoshita, Hideo Fujiwara, Kewal K. Saluja, 1983, IEEE Transactions on Computers.

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2009, IPSJ Trans. Syst. LSI Des. Methodol..

ランダムアクセススキャン : テスト時消費電力,テストデータ量,テスト時開削減法(VLSI設計とテスト)

Dong Hyun Baik, Kewal K. Saluja, 梶原誠司, 2004 .

Testing flash memories

Kewal K. Saluja, Mohammad Gh. Mohammad, Alex S. Yap, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Analysis and test procedures for NOR flash memory defects

Kewal K. Saluja, Mohammad Gh. Mohammad, K. Saluja, 2008, Microelectron. Reliab..

On-chip testing of random access memories

Kewal K. Saluja, 1994, J. Electron. Test..

A concurrent testing technique for digital circuits

Kewal K. Saluja, Charles R. Kime, Rajiv Sharma, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testing Flash Memories for Tunnel Oxide Defects

Kewal K. Saluja, Mohammad Gh. Mohammad, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Moments Based Blind Calibration in Mobile Sensor Networks

Parameswaran Ramanathan, Chao Wang, Kewal K. Saluja, 2008, 2008 IEEE International Conference on Communications.

Test Pattern Generation for API Faults in RAM

Kozo Kinoshita, Kewal K. Saluja, 1985, IEEE Transactions on Computers.

Fault diagnosis in loop-connected systems

Brian D. O. Anderson, Kewal K. Saluja, 1980, Inf. Sci..

Thermal Extension of the Total Bandwidth Server

Parameswaran Ramanathan, Kewal K. Saluja, Rehan Ahmed, 2015, 2015 28th International Conference on VLSI Design.

Test cost reduction using partitioned grid random access scan

Dong Hyun Baik, Kewal K. Saluja, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Fault simulation and test generation for clock delay faults

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems

Parameswaran Ramanathan, Kewal K. Saluja, Rehan Ahmed, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Routing TCP Flows in Underwater Mesh Networks

Parameswaran Ramanathan, Kewal K. Saluja, Chin-Ya Huang, 2011, IEEE Journal on Selected Areas in Communications.

Connected Barrier Coverage on a Narrow Band: Analysis and Deployment

Yen-Ting Lin, Parameswaran Ramanathan, Kewal K. Saluja, 2010, 2010 7th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks (SECON).

Random pattern testing for sequential circuits revisited

Kewal K. Saluja, Lama Nachman, Shambhu J. Upadhyaya, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

Modeling Detection Latency with Collaborative Mobile Sensing Architecture

Parameswaran Ramanathan, Kewal K. Saluja, Tai-Lin Chin, 2009, IEEE Transactions on Computers.

Compaction of Test Vectors for IDDQ Testing of Sequential Circuits

Kewal K. Saluja, Yuzo Takamatsu, Yoshinobu Higami, 2000 .

Vulnerability of Surveillance Networks to Faults

Parameswaran Ramanathan, Kewal K. Saluja, Thomas Clouqueur, 2006, Int. J. Distributed Sens. Networks.

An Efficient Method for Computation of Signatures

Kewal K. Saluja, Chin-Foo See, 1992, The Fifth International Conference on VLSI Design.

Multiple Faults in Reed-Muller Canonic Networks

Sudhakar M. Reddy, Kewal K. Saluja, 1972, SWAT.

Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies

Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test application time reduction for scan based sequential circuits

Kewal K. Saluja, Hao Zheng, Rajiv Jain, 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

Power Efficient Redundant Execution for Chip Multiprocessors

Erik G. Larsson, Kewal K. Saluja, Pramod Subramanyan, 2009 .

Compact Dictionaries for Reducing Compute Time in Adaptive Diagnosis

Kewal K. Saluja, Yoshinobu Higami, Hiroshi Takahashi, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

A new method towards achieving global optimality in technology mapping

Xiaoqing Wen, Kewal K. Saluja, 1996, Proceedings of International Conference on Computer Aided Design.

Software-based delay fault self-testing of pipelined processor cores

Kewal K. Saluja, Virendra Singh, Michiko Inoue, 2004 .

Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks

Parameswaran Ramanathan, Kewal K. Saluja, Rehan Ahmed, 2014, 2014 26th Euromicro Conference on Real-Time Systems.

Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults

Kewal K. Saluja, Manoj Franklin, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Transient Fault Resilient QR Factorization on GPUs

Parameswaran Ramanathan, Kewal K. Saluja, Felix Loh, 2015, FTXS@HPDC.

Optimizing device size for soft error resilience in sub-micron logic circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Fault detection in combinational circuits using Gunn effect logic devices

Kewal K. Saluja, F. J. Lidgey, 1981 .

Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling

Kewal K. Saluja, Spencer K. Millican, 2014, J. Electron. Test..

Fault Models and Test Procedures for Flash Memory Disturbances

Kewal K. Saluja, Mohammad Gh. Mohammad, Alex S. Yap, 2001, J. Electron. Test..

Pattern sensitive fault testing of RAMs with built-in ECC

Kewal K. Saluja, Manoj Franklin, 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

Power constraint scheduling of tests

Vishwani D. Agrawal, Kewal K. Saluja, Richard M. Chou, 1994, Proceedings of 7th International Conference on VLSI Design.

An Alternative to Scan Design Methods for Sequential Machines

Kewal K. Saluja, Ramaswami Dandapani, 1986, IEEE Transactions on Computers.

Department of Electrical and Computer Engineering University of Wisconsin{Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2009-2010

Kewal K. Saluja, 2010 .

Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method

Parameswaran Ramanathan, Kewal K. Saluja, Felix Loh, 2021, Journal of Electronic Testing.

PROCESSING FOR TARGET DETECTION , LOCALIZATION , AND TRACKING

Parameswaran Ramanathan, Yu Hen Hu, Kewal K. Saluja, 2002 .

Motivating Commodity Multi-Core Processor Design for System-level Error Protection

Norman P. Jouppi, Kewal K. Saluja, Parthasarathy Ranganathan, 2022 .

Test Scheduling for Circuits in Micron to Deep Submicron Technologies

Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao, 2010 .