S. Wu

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies

D. Schepis, D. Yee, S. Wu, 1997 .

A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

S. Narasimha, J. Adkisson, E. Maciejewski, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications

M. Soyuer, S. Subbanna, B.S. Meyerson, 1995, Proceedings of Bipolar/Bicmos Circuits and Technology Meeting.

A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAM

R. Flaker, S. Ratanaphanyarat, E. Leobandung, 1997, International Electron Devices Meeting. IEDM Technical Digest.