Yu-Shih Su

Synthesis of a timing-error detection architecture

TingTing Hwang, Shih-Chieh Chang, Yu-Shih Su, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Fault-tolerant 3D clock network

Yiyu Shi, Shih-Chieh Chang, Chiao-Ling Lung, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs

Yiyu Shi, Shih-Chieh Chang, Chiao-Ling Lung, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Benchmarking for research in power delivery networks of three-dimensional integrated circuits

Chun Zhang, Yiyu Shi, Ding-Ming Kwai, 2013, ISPD '13.

Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Wing-Kai Hon, Shih-Chieh Chang, Yeong-Jar Chang, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

An Efficient Mechanism for Performance Optimization of Variable-Latency Designs

Shih-Chieh Chang, Malgorzata Marek-Sadowska, Yu-Shih Su, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction

Tao Wang, Yiyu Shi, Ding-Ming Kwai, 2012, 17th Asia and South Pacific Design Automation Conference.

Performance Optimization Using Variable-Latency Design Style

Shih-Chieh Chang, Malgorzata Marek-Sadowska, Yu-Shih Su, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

Wing-Kai Hon, Shih-Chieh Chang, Yeong-Jar Chang, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synthesis of a novel timing-error detection architecture

TingTing Hwang, Shih-Chieh Chang, Yu-Shih Su, 2008, TODE.