C.-J.R. Shi

A high-throughput low-power fully parallel 1024-bit 1/2 -rate low density parity check code decoder in 3D integrated circuits

C. Wakayama, N. Jangkrajarng, L. Zhou, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Layout compaction for yield optimization via critical area minimization

C. Shi, C.-J.R. Shi, Y. Bourai, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Efficient DDD-based term generation algorithm for analog circuit behavioral modeling

S.X.-D. Tan, C. Shi, S. Tan, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

Symbolic model order reduction

Guoyong Shi, C.-J.R. Shi, B. P. Hu, 2003, Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation.

A layout dependent and bias independent scalable substrate model for CMOS RF transistors

K. Mayaram, C.-J.R. Shi, R. Suravarapu, 2002, Proceedings RAWCON 2002. 2002 IEEE Radio and Wireless Conference (Cat. No.02EX573).

Parametric reduced order modeling for interconnect analysis

Guoyong Shi, C.-J.R. Shi, 2004 .