W. Tsai

发表

Demonstration of $L_{g} \sim \hbox{55}\ \hbox{nm}$ pMOSFETs With $\hbox{Si/Si}_{0.25}\hbox{Ge}_{0.75}/\hbox{Si}$ Channels, High $I_{\rm on}/I_{\rm off}\ (≫ \hbox{5} \times \hbox{10}^{4})$ , and Controlled Short Channel Effects (SCEs)

Hsing-Huang Tseng, S. Datta, R. Jammy, 2008, IEEE Electron Device Letters.

Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

S. De Gendt, M. Heyns, M. Caymax, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Demonstration of High-Performance PMOSFETs Using $ \hbox{Si}$–$\hbox{Si}_{x}\hbox{Ge}_{1 - x}$ –$\hbox{Si}$ Quantum Wells With High- $\kappa$/Metal-Gate Stacks

R. Jammy, P. Majhi, R. Choi, 2008, IEEE Electron Device Letters.

Charge Trapping and Wearout Characteristics of Self-Aligned Enhancement-Mode GaAs n-MOSFET with Si Interface Passivation Layer and HfO2 Gate Oxide

S. Koveshnikov, J.C. Lee, V. Tokranov, 2008, 2008 IEEE Compound Semiconductor Integrated Circuits Symposium.

Surface preparation and interfacial stability of high-k dielectrics deposited by atomic layer chemical vapor deposition

Wilfried Vandervorst, Marc Heyns, Matty Caymax, 2003 .

Scaling of high-k dielectrics towards sub-1nm EOT

S. De Gendt, D. Pique, S. Van Elshocht, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

R. Jammy, P. Majhi, J. Lee, 2008, 2008 Symposium on VLSI Technology.

Self-aligned inversion channel In0.53Ga0.47As N-MOSFETs with ALD-Al2O3 and MBE-Al2O3/Ga2O3(Gd2O3) as gate dielectrics

Shawn S. H. Hsu, H. C. Chiu, T. D. Lin, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node

R. Jammy, P. Majhi, R. Choi, 2007, 2007 IEEE International Electron Devices Meeting.

Issues, achievements and challenges towards integration of high-k dielectrics

Richard Carter, Guido Groeseneken, L. Pantisano, 2002 .

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs

S. De Gendt, L. Pantisano, A. Kerber, 2003, IEEE International Electron Devices Meeting 2003.

Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO/sub 2/ and HfO/sub 2/

Y. Nishi, P. Majhi, L. Colombo, 2005, IEEE Electron Device Letters.

Addressing the gate stack challenge for high mobility InxGa1-xAs channels for NFETs

S. Koveshnikov, S. Datta, V. Tokranov, 2008, 2008 IEEE International Electron Devices Meeting.

High performing 8 A EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown (SPER) junctions

S. De Gendt, S. Severi, G. Groeseneken, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Self-Aligned n- and p-channel GaAs MOSFETs on Undoped and P-type Substrates Using HfO2 and Silicon Interface Passivation Layer

S. Koveshnikov, J.C. Lee, V. Tokranov, 2006, 2006 International Electron Devices Meeting.