Shih-Chang Chen

5nm-gate nanowire FinFET

Chenming Hu, Yee-Chia Yeo, Mong-Song Liang, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Limitation of sputtered adhesion layer thickness for blanket CVD W in very high aspect contact filling

M. Yoshimaru, M. Ino, Shih-Chang Chen, 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ High- $\kappa$ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Bing-Yue Tsui, Mong-Song Liang, Mao-Chieh Chen, 2007, IEEE Transactions on Electron Devices.

Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation

Chih-Wei Yang, Mong-Song Liang, Tze-Liang Lee, 2002 .

A 65nm node strained SOI technology with slim spacer

Chenming Hu, Tsai-Sheng Gau, Yee-Chia Yeo, 2003, IEEE International Electron Devices Meeting 2003.

High-Performance PMOS Devices on (110)/<111'> Substrate/Channel with Multiple Stressors

Mong-Song Liang, H.C.-H. Wang, Tze-Liang Lee, 2006, 2006 International Electron Devices Meeting.