H. Mair

2009 VLSI Circuits Short Course Program "Energy Management for Green SoC's and SiP's"

Elad Alon, M. Ikeda, B. Nikolic, 2009 .

Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

L. Bouetel, C. Raibaut, H. Mair, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations

H. Mair, P. Royannez, D. Scott, 2007, 2007 IEEE Symposium on VLSI Circuits.

Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor

L. Bouetel, C. Raibaut, H. Mair, 2006, 2006 IEEE International Conference on IC Design and Technology.

90nm low leakage SoC design techniques for wireless applications

Uming Ko, L. Bouetel, C. Raibaut, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A 65 nm CMOS technology for mobile and digital signal processing applications

D. Mosher, H. Mair, D. Scott, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

An architecture of high-performance frequency and phase synthesis

Liming Xiu, H. Mair, 2000, IEEE Journal of Solid-State Circuits.

An ASIC design flow of deep submicron succeeds on first pass

Liming Xiu, H. Mair, 1998, 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105).