Ming-Zhang Kuo

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC

Sang H. Dhong, Wei Hwang, Kevin Huang, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB

Sang H. Dhong, Osamu Takahashi, Min-Jer Wang, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology

Sang H. Dhong, Wei Hwang, Kevin Huang, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 4-GHz universal high-frequency on-chip testing platform for IP validation

Sang H. Dhong, Kevin Huang, Min-Jer Wang, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

Sang H. Dhong, Wei Hwang, Kevin Huang, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.