K. Donnelly

A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

J. Wei, K. Donnelly, Yiu-Fai Chan, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS

N. Nguyen, K. Donnelly, Y. Frans, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell

V. Stojanovic, A. Ho, F. Chen, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

J. Wei, S. Sidiropoulos, K. Donnelly, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).