M. Nishio

High Reliability Trench Isolation Technology with Elevated Field Oxide Structure for Sub-Quarter Micron CMOS Devices

Takashi Nakabayashi, A. Kanda, Toshiki Yabu, 1996 .

A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells

K. Hashimoto, H. Umimoto, A. Asai, 1992, 1992 International Technical Digest on Electron Devices Meeting.

A high-speed bipolar LSI process using self-aligned double diffusion polysilicon technology

S. Kameyama, T. Komeda, M. Nishio, 1986, 1986 International Electron Devices Meeting.