Pin Su

发表

Impacts of wire-LER on Nanowire MOSFET devices, subthreshold SRAM and logic circuits

Ching-Te Chuang, Ming-Long Fan, Ming-Fu Tsai, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Design and Analysis of Robust Tunneling FET SRAM

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, IEEE Transactions on Electron Devices.

Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors

Pin Su, Wei-Xiang You, P. Su, 2017, IEEE Transactions on Electron Devices.

Comparison of differential and large-signal sensing scheme for subthreshold/superthreshold FinFET SRAM considering variability

Ching-Te Chuang, Ming-Long Fan, Yin-Nien Chen, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

UTB GeOI 6T SRAM cell and sense amplifier considering BTI reliability

Ching-Te Chuang, Vita Pi-Ho Hu, Pin Su, 2015, 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Investigation of stability and AC performance of sub-threshold FinFET SRAM

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, IEEE Transactions on Electron Devices.

Comprehensive Noise Characterization and Modeling for 65-nm MOSFETs for Millimeter-Wave Applications

Guo-Wei Huang, Kun-Ming Chen, Pin Su, 2010, IEEE Transactions on Microwave Theory and Techniques.

Investigation of single-trap-induced random telegraph noise for tunnel FET based devices, 8T SRAM cell, and sense amplifiers

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Impact of work function design on the stability and performance of Ultra-Thin-Body SOI subthreshold SRAM

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach

Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, 2011, IEEE Transactions on Electron Devices.

Exploration and evaluation of TCAM with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications

Ching-Te Chuang, Yin-Nien Chen, Pin Su, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation

Chenming Hu, Pin Su, Wei-Xiang You, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Stability analysis for UTB GeOI 6T SRAM cells considering NBTI and PBTI

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015, 2015 International Symposium on VLSI Technology, Systems and Applications.

Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors

Pin Su, Wei-Xiang You, 2017, 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).

A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET

Chenming Hu, Pin Su, Wei-Xiang You, 2020, IEEE Journal of the Electron Devices Society.

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

Chenming Hu, Pin Su, Wei-Xiang You, 2019, IEEE Transactions on Electron Devices.

A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Impacts of work function variation and line edge roughness on hybrid TFET-MOSFET monolithic 3D SRAMs

Ching-Te Chuang, Pin Su, Jian-Hao Wang, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM Model

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2010, IEEE Transactions on Electron Devices.

Investigation of Static Noise Margin of FinFET SRAM cells in sub-threshold region

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2009, 2009 IEEE International SOI Conference.

Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs

Pin Su, Wei-Xiang You, Ho-Pei Lee, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Disturb-free Independently-controlled-Gate 7T FinFET SRAM cell

Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, IEEE Electron Device Letters.

Simulation and Investigation of Random Grain-Boundary-Induced Variabilities for Stackable NAND Flash Using 3-D Voronoi Grain Patterns

Pin Su, P. Su, Ching-Wei Yang, 2014, IEEE Transactions on Electron Devices.

Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, IEEE Transactions on Nanotechnology.

Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS

Chenming Hu, Pin Su, Y. Komatsu, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors

Pin Su, Wei-Xiang You, Chih-Peng Tsai, 2018, IEEE Transactions on Electron Devices.

Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015, IEEE Transactions on Electron Devices.

Impact of Process-Induced Strain on Coulomb Scattering Mobility in Short-Channel n-MOSFETs

Pin Su, K. Goto, W.P.N. Chen, 2008, IEEE Electron Device Letters.

Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2016, IEEE Transactions on Electron Devices.

On the prediction of geometry-dependent floating-body effect in SOI MOSFETs

Pin Su, Wei Lee, 2005 .

Investigation of electrostatic integrity for ultra-thin-body GeOI MOSFET using analytical solution of Poisson's equation

Vita Pi-Ho Hu, Pin Su, Yu-Sheng Wu, 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, IEEE Transactions on Electron Devices.

Tendency for full depletion due to gate tunneling current

Mansun Chan, Chenming Hu, Pin Su, 2002, 2002 IEEE International SOI Conference.

Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETs

Vita Pi-Ho Hu, Pin Su, Yu-Sheng Wu, 2012, IEEE Transactions on Electron Devices.

Impacts of intrinsic device variations on the stability of FinFET subthreshold SRAMs

Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, 2011, 2011 IEEE International Conference on IC Design & Technology.

Device Structural Effects on Negative-Capacitance FETs

Pin Su, Wei-Xiang You, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Impact of Aspect Ratio on the Subthreshold RTN Amplitude of Multi-Gate MOSFETs

Ming-Long Fan, Pin Su, B. K. Y. Lu, 2011 .

Investigation of Electrostatic Integrity for Ultrathin-Body Germanium-On-Nothing MOSFET

Vita Pi-Ho Hu, Pin Su, Yu-Sheng Wu, 2011, IEEE Transactions on Nanotechnology.

80nm SOI CMOS parameter extraction for BSIMPD

Toshihiro Sugii, Chenming Hu, Pin Su, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

Investigation and Simulation of Work-Function Variation for III–V Broken-Gap Heterojunction Tunnel FET

Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, 2015, IEEE Journal of the Electron Devices Society.

Impacts of single trap induced random telegraph noise on finfet devices and SRAM cell stability

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2011, IEEE 2011 International SOI Conference.

Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs

Pin Su, Ken-Ichi Goto, Carlos H. Diaz, 2009 .

Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures

Pin Su, Wei-Xiang You, P. Su, 2018, IEEE Transactions on Electron Devices.

Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015, IEEE Transactions on Electron Devices.

On the Enhanced Impact Ionization in Uniaxial Strained p-MOSFETs

Pin Su, Jack J.-Y. Kuo, 2007, IEEE Electron Device Letters.

BSIM Model Research and Recent Progress 3

Ali Niknejad, Pin Su, Chan Mansun, 2006 .

Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs

Vita Pi-Ho Hu, Pin Su, Yu-Sheng Wu, 2012, IEEE Transactions on Nanotechnology.

Investigation of analogue performance for process-induced-strained PMOSFETs

Pin Su, W.P.-N. Chen, Jack J.-Y. Kuo, 2007 .

Investigation of Temperature-Dependent High-Frequency Noise Characteristics for Deep-Submicrometer Bulk and SOI MOSFETs

Guo-Wei Huang, Pin Su, Sheng-Chun Wang, 2012, IEEE Transactions on Electron Devices.

Investigation of Switching-Time Variations for Nanoscale MOSFETs Using the Effective-Drive-Current Approach

Ming-Long Fan, Pin Su, Yu-Sheng Wu, 2010, IEEE Electron Device Letters.

Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells—An Assessment Based on Analytical Solutions of Poisson's Equation

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2009, IEEE Transactions on Electron Devices.

Self-heating enhanced impact ionization in SOI MOSFETs

Toshihiro Sugii, Chenming Hu, Pin Su, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

Sensitivity of Multigate mosfets to Process Variations–-An Assessment Based on Analytical Solutions of 3-D Poisson's Equation

Pin Su, Yu-Sheng Wu, P. Su, 2008, IEEE Transactions on Nanotechnology.

Evaluation of static noise margin and performance of 6T FinFET SRAM cells with asymmetric gate to source/drain underlap devices

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2010, 2010 IEEE International SOI Conference (SOI).

Impact of surface orientation on Vth variability of FinFET

Ming-Long Fan, Pin Su, Yu-Sheng Wu, 2010, 2010 Silicon Nanoelectronics Workshop.

Sensitivity of Gate-All-Around Nanowire MOSFETs to Process Variations—A Comparison With Multigate MOSFETs

Pin Su, Yu-Sheng Wu, P. Su, 2008, IEEE Transactions on Electron Devices.

On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs

Guo-Wei Huang, Pin Su, Sheng-Chun Wang, 2007, IEEE Microwave and Wireless Components Letters.

Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications

Pin Su, Wei-Xiang You, Kuei-Yang Tseng, 2019, 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Variability analysis of UTB SOI subthreshold SRAM considering Line-Edge Roughness, Work Function Variation and temperature sensitivity

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2011, 2011 IEEE International Conference on IC Design & Technology.

Comprehensive analysis of UTB GeOI logic circuits and 6T SRAM cells considering variability and temperature sensitivity

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2011, 2011 International Electron Devices Meeting.

Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using a Voronoi Approach

Ming-Long Fan, Pin Su, Shao-Heng Chou, 2013, IEEE Transactions on Electron Devices.

Analytical Quantum-Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold Region

Pin Su, Yu-Sheng Wu, P. Su, 2009, IEEE Transactions on Electron Devices.

Investigation of Electrostatic Integrity for Ultra-Thin-Body GeON MOSFET

Vita Pi-Ho Hu, Pin Su, YewChung Sermon Wu, 2009 .

Subthreshold FinFET SRAM cell optimization considering surface-orientation dependent variability

Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

RF Extrinsic Resistance Extraction Considering Neutral-Body Effect for Partially-Depleted SOI MOSFETs

Guo-Wei Huang, Pin Su, Sheng-Chun Wang, 2006, 2006 International Symposium on VLSI Technology, Systems, and Applications.

Circuit performance of double-gate SOI CMOS

Ali M. Niknejad, Mansun Chan, Chenming Hu, 2003, International Semiconductor Device Research Symposium, 2003.

Impact of Quantum Confinement on Short-Channel Effects for Ultrathin-Body Germanium-on-Insulator MOSFETs

Vita Pi-Ho Hu, Pin Su, Yu-Sheng Wu, 2011, IEEE Electron Device Letters.

Variability Analysis of Sense Amplifier for Subthreshold Ultra-Thin-Body SOI SRAM Applications

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012 .

Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, IEEE Transactions on Electron Devices.

Temperature Dependence of High Frequency Noise Behaviors for RF MOSFETs

Guo-Wei Huang, Pin Su, Sheng-Chun Wang, 2008, IEEE Microwave and Wireless Components Letters.