Bahram Rashidi

发表

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

Bahram Rashidi, Mohammad Abedini, 2019, J. Circuits Syst. Comput..

Design of a low-power and low-cost booth-shift/add multiplexer-based multiplier

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication

Bahram Rashidi, 2020, J. Hardw. Syst. Secur..

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2016, Integr..

High-speed and pipelined finite field bit-parallel multiplier over GF(2m) for elliptic curve cryptosystems

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2014, 2014 11th International ISC Conference on Information Security and Cryptology.

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Bahram Rashidi, Bahram Rashidi, 2020, IET Circuits Devices Syst..

Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA

Bahram Rashidi, Bahman Rashidi, 2013 .

High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers

Bahram Rashidi, 2019, Microelectron. J..

Efficient hardware implementations of point multiplication for binary Edwards curves

Bahram Rashidi, Bahram Rashidi, 2018, Int. J. Circuit Theory Appl..

A Survey on Hardware Implementations of Elliptic Curve Cryptosystems pdf

Bahram Rashidi, Bahram Rashidi, 2017, ArXiv.

Compact and efficient structure of 8-bit S-box for lightweight cryptography

Bahram Rashidi, Bahram Rashidi, 2021, Integr..

High‐throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

Bahram Rashidi, Bahram Rashidi, 2019, Int. J. Circuit Theory Appl..

High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2016, Microelectron. J..

FPGA Based A New Low Power and Self-Timed AES 128-bit Encryption Algorithm for Encryption Audio Signal

Bahram Rashidi, Bahman Rashidi, 2012 .

Authentication issues for cloud applications

Bahram Rashidi, 2019 .

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

Bahram Rashidi, 2020, IET Comput. Digit. Tech..

An adaptive multi-objective optimization method for optimum design of distribution networks

Bahram Rashidi, Mohammad Abedini, Mohamad Mohamadi, 2020, Engineering Optimization.

High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m)

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2016, IACR Cryptol. ePrint Arch..

A high-speed multiplexer-based fine-grain pipelined architecture for digital fuzzy logic controllers

Bahram Rashidi, Sayed Masoud Sayedi, S. Sayedi, 2015 .

Low Power FPGA Implementation of Digital FIR Filter Based on Low Power Multiplexer Base Shift/Add Multiplier

Bahram Rashidi, Bahman Rashidi, Farshad Mirzaei, 2013 .

Low-Cost and Optimized Two Layers Embedded Board Based on ATmega32L Microcontroller and Spartan-3 FPGA

Bahram Rashidi, 2013 .

Low-Cost and Fast Hardware Implementations of Point Multiplication on Binary Edwards Curves

Bahram Rashidi, Bahram Rashidi, 2018, Electrical Engineering (ICEE), Iranian Conference on.

FPGA implementation of optimized the 64-bit RC5 encryption algorithm

Bahram Rashidi, Bahram Rashidi, 2012 .

Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher

Bahram Rashidi, 2020, Int. J. Circuit Theory Appl..

Implementation of a High Speed Technique for Character Segmentation of License Plate Based on Thresholding Algorithm

Bahram Rashidi, Bahman Rashidi, Bahram Rashidi, 2012 .

A Two Layers Novel Low-Cost and Optimized Embedded Board Based on TMS320C6713 DSP and Spartan-3 FPGA

Bahram Rashidi, Ghader Karimian, 2013 .

High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA

Bahram Rashidi, Bahram Rashidi, 2013, IET Signal Process..

High-speed hardware implementation of Gaussian normal basis inversion algorithm over F2m

Bahram Rashidi, Bahram Rashidi, 2017, Microelectron. J..

High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2017, IACR Cryptol. ePrint Arch..

Design and implementation of low power digital FIR filter based on low power multipliers and adders on xilinx FPGA

Bahram Rashidi, Bahman Rashidi, Majid Pourormazd, 2011, 2011 3rd International Conference on Electronics Computer Technology.

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2014, Microelectron. J..

Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m )

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2016, IET Comput. Digit. Tech..

Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2017, IET Circuits Devices Syst..

FPGA Implementation of Digital Controller for Simple and Maximum Boost Control of Three Phase Z-Source Inverter

Bahram Rashidi, 2013 .

Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2017, IET Circuits Devices Syst..

Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2015, IACR Cryptol. ePrint Arch..

High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2 m )

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2017, IET Inf. Secur..

Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers

Bahram Rashidi, 2019, IET Circuits Devices Syst..

A High Speed and Low Power Image Encryption with 128-Bit AES Algorithm

Bahram Rashidi, Ali Farmani, G. H. Karimian, 2012 .

High Performance FPGA Based Digital Space Vector PWM Three Phase Voltage Source Inverter

Mehran Sabahi, Bahram Rashidi, 2013 .

Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2015, ISC Int. J. Inf. Secur..

Efficient hardware structure for extended Euclidean-based inversion over F 2 m

Bahram Rashidi, 2019, IET Comput. Digit. Tech..

Fast and pipelined bit-parallel montgomery multiplication and squaring over GF(2m)

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2015, 2015 12th International Iranian Society of Cryptology Conference on Information Security and Cryptology (ISCISC).

Efficient full data-path width and serialized hardware structures of SPONGENT lightweight hash function

Bahram Rashidi, Bahram Rashidi, 2021, Microelectron. J..

Lightweight 8‐bit S‐box and combined S‐box/S‐box−1 for cryptographic applications

Bahram Rashidi, Bahram Rashidi, 2021, Int. J. Circuit Theory Appl..

Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things

Bahram Rashidi, Bahram Rashidi, 2021, IET Comput. Digit. Tech..