J. V. Francés

Hardware implementation of real-time Extreme Learning Machine in FPGA: Analysis of precision, resource occupation and performance

Marek Wegrzyn, José V. Francés, Manuel Bataller-Mompeán, 2016, Comput. Electr. Eng..

Simplified spiking neural network architecture and STDP learning algorithm applied to image classification

M. Bataller-Mompeán, J. V. Francés, A. R. Muñoz, 2015, EURASIP J. Image Video Process..

Fast spiking neural network architecture for low-cost FPGA devices

Taras Iakymchuk, José V. Francés, Manuel Bataller-Mompeán, 2012, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

Support Tool for the Combined Software/Hardware Design of On-Chip ELM Training for SLFF Neural Networks

Marek Wegrzyn, José V. Francés, Manuel Bataller-Mompeán, 2016, IEEE Transactions on Industrial Informatics.

Design environment for hardware generation of SLFF neural network topologies with ELM training capability

Marek Wegrzyn, José V. Francés, Manuel Bataller-Mompeán, 2015, 2015 IEEE 13th International Conference on Industrial Informatics (INDIN).

Ventricular Fibrillation and Tachycardia detection from surface ECG using time-frequency representation images as input dataset for machine learning

Azeddine Mjahad, José V. Francés, Manuel Bataller-Mompeán, 2017, Comput. Methods Programs Biomed..